Self-clocking system

• US 4,993,048 A
• Filed: 04/18/1990
• Issued: 02/12/1991
• Est. Priority Date: 04/18/1990
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Williams, Bruce H., Arbanas, Glenn A., Snyder, Valjean P.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US07/510,526
• Time in Patent Office: 300 Days
• Field of Search: 375/97, 375/119, 375/120, 375/121, 370/84, 360/51, 331/1 R, 331/1 A, 331/17, 331/25, 331/34, 328/133, 328/135, 328/72, 328/73, 328/63, 307/511, 307/521, 307/522
• US Class Current: 375/344
• CPC Class Codes: H04L 2027/0024 at the receiver end
• CPC Class Codes: H04L 2027/0063 Elements of loops
• CPC Class Codes: H04L 25/0262 Arrangements for detecting the data rate of an incoming signal
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Abstract

Self-clocking system for demodulating phase encoded data automatically tracks incoming data rate changes by using information from a bit synchronizer to track the incoming base band data signal.

Claims

1. A self-clocking system for demodulating phase encoded data signals which have a variable frequency, comprising in combination;

means for generating a baseband data signal;

means coupling said baseband signal to an input of a filter having a pass band matched to the frequency of said phase encoded data signal, said filter producing a filtered output data signal in response to said baseband signal input;

means for comparing said filtered output data signal with a clock signal, said comparing means producing an output voltage which is a function of a phase difference between said filtered output data signal and said clock signal;

means for coupling the output of said filter to the input of said comparing means;

a variable counter;

a voltage controlled oscillator, means for coupling said comparing means output voltage to the input of said voltage controlled oscillator;

means for coupling an output of said voltage controlled oscillator to an input of said variable counter, which counter divides the output of said oscillator by a count "N" to generate said clock signal; and

a controller responsive to said comparing means output to vary said pass band of said filter to match said phase encoded data signal frequency and to vary "N" to maintain the voltage input to said voltage controlled oscillator within the deviation band width of said voltage controlled oscillator.

2. A self-clocking system for demodulating phase encoded data signals which have a variable rate, as in claim 1 wherein said controller computes said data frequency from the voltage controlled oscillator input voltage and the count "N" in said counter.

3. A self-clocking system for demodulating phase encoded data signals which have a variable rate, as in claim 1, wherein values of "N" are larger than the voltage controlled oscillator center frequency to deviation band width ratio.