Method for manufacturing a control plate for a lithographic device

• US 4,994,336 A
• Filed: 05/17/1989
• Issued: 02/19/1991
• Est. Priority Date: 05/31/1988
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Schnakenberg, Uwe, Benecke, Wolfgang, Lischke, Burkhard
• Primary Examiner(s): Dees, Jose G.
• Application Number:
  US07/353,063
• Time in Patent Office: 643 Days
• Field of Search: 430/5, 430/321, 430/323, 430/324, 250/492.22, 250/492.21, 250/505.1
• US Class Current: 430/5
• CPC Class Codes: H01J 37/1477 electrostatic
• CPC Class Codes: H01J 9/02 Manufacture of electrodes or electrode systems

Abstract

A method for manufacturing a control plate for a lithographic device. The control plate manufactured with a method of the present invention is essentially composed of a semiconductor substrate having an opening for the passage of particle probes emanating from a multi-beam source and of a corresponding plurality of deflection elements that are connected via bond pads and connecting lines to the electronics of the lithographic device that generates control signals. Lithographic methods and voltaic shaping techniques are utilized for the manufacture of the deflection elements located on the semiconductor substrate which is coated with a dielectric.

Claims

1. A method for manufacturing a control plate for a lithographic apparatus, whereby the control plate charged with a plurality of particle probes (14, 14'"'"') has a semiconductor substrate (1) having an opening (10) for the passage of the particle probes (14, 14'"'"') and has a plurality of deflection elements (9, 9'"'"') for individually deflecting the particle probes (14, 14'"'"'), comprising the steps of:

providing on a front side of the semiconductor substrate (1) a first dielectric layer (2) and providing on a back side of the semiconductor substrate (1) a second dielectric layer (3);

depositing a metallic layer (4) on the first dielectric layer (2);

structuring the second dielectric layer (3) according to the geometry of the opening (10) to be produced in the semiconductor substrate (1);

lithographically transferring the geometry and arrangement of the deflection elements (9, 9'"'"') to be produced onto a photoresist layer (8) applied on the metallic layer (4), whereby the thickness of the photoresist layer (8) exceeds the height of the deflection elements (9, 9'"'"');

voltaically filling up the depressions generated in the photoresist layer (8) to the desired height of the deflection elements (9, 9'"'"');

removing the photoresist layer (8);

producing the opening (10) by etching the back side of the semiconductor substrate (1); and

removing the metallic layer (4) and the first dielectric layer (2) in the region of the opening (10).

3. The method according to claim 1 wherein the semiconductor substrate (1) is composed of silicon, and the silicon has a (1, 0, 0) orientation.

4. The method according to claim 1 wherein the semiconductor substrate (1) is composed of silicon, and the silicon has a (1, 1, 0) orientation.

2. A method for manufacturing a control plate for a lithographic device, whereby the control plate charged with a plurality of particle probes (14, 14'"'"') has a semiconductor substrate (1) having an opening (10) for the passage of the particle probes (14, 14'"'"') and has a plurality of deflection elements (9, 9'"'"') for individually deflecting the particles probes (14 14'"'"'), comprising the steps of:

providing on a front side of the semiconductor substrate (1) a first dielectric layer (2) and providing on a back side of the semiconductor substrate a second dielectric layer (3);

depositing a metallic layer (4) on the first dielectric layer (2);

structuring the second dielectric layer (3) according to the geometry of the opening (10) to be generated in the semiconductor substrate (1);

coating the metallic layer with a first (11) and a second intermediate layer (12), whereby the thickness of the first intermediate layer (11) is dimensioned such that it exceeds the height of the deflection elements (9, 9'"'"') to be formed;

lithographically transferring the geometry and arrangement of the deflection elements (9, 9'"'"') to be generated onto a photoresist layer (5) applied on the second intermediate layer (12);

transferring the structure of the photoresist layer (5) by an etching of the first and second intermediate layers (11,

     12);

voltaically filling the depressions generated in the first intermediate layer (11) up to the height of the deflection elements (9, 9'"'"');

removing the photoresist layer (5) and the first and second intermediate layers (11,

     12);

generating the opening (10) by anisotropic etching of the semiconductor substrate at the back side of the semiconductor substrate; and

removing the first dielectric layer (2) and the metallic layer (4) in the region of the opening (10).

5. The method according to claim 2 wherein the semiconductor substrate (1) is composed of silicon, and the silicon has a (1, 0, 0) orientation.

6. The method according to claim 2 wherein the semiconductor substrate (1) is composed of silicon, and the silicon has a (1, 1, 0) orientation.