Method of making an electrically programmable, electrically erasable memory array cell

• US 4,994,403 A
• Filed: 12/28/1989
• Issued: 02/19/1991
• Est. Priority Date: 12/28/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gill, Manzur
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/457,990
• Time in Patent Office: 418 Days
• Field of Search: 437/43, 437/48, 437/49, 437/50, 437/52, 437/61, 357/23.5
• US Class Current: 438/261
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective drain regions (30a, 30b), a shared source region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) which may be programmed by hot electron injection and erased by Fowler-Nordheim electron tunneling through respective tunneling oxide windows (40a, 40b) overlying a portion of source region (28) adjacent respective channels (38a, 38b). A wordline or control gate conductor (62) is insulatively disposed adjacent the floating gates (46a, 46b) to program or erase.

Claims

1. A method for fabricating at least first and second electrically erasable and programmable memory cells at a face of a semiconductor layer having a first conductivity type, comprising the steps of:

selectively doping the semiconductor layer with a dopant of a second conductivity type opposite the first conductivity type to create a drain region of the first cell, a shared source region spaced from the drain region of the first cell by a channel region of the first cell, and a drain region of the second cell spaced from the source region by a channel region of the second cell;

differentially growing an insulator layer over the face to create thick insulator regions over the source and drain regions, and a relatively thin insulator layer in between the source region and the drain regions;

selectively removing the thin insulator layer to expose first and second window areas on the source region adjacent the channel regions of the respective first and second cells;

forming a first conductive layer over the face;

selectively etching the first conductive layer to define first and second floating gate conductors, each formed over a respective thin window insulator and the channel adjacent the respective thin window insulator; and

forming a control gate conductor insulatively adjacent the floating gate conductors.

2. The method of claim 1, and further comprising the steps of:

after said step of forming the first conductive layer over the face, forming an oxide layer on the first conductive layer;

forming a nitride layer on the oxide layer; and

forming a second oxide layer on the nitride layer to create a three-insulator oxide-nitride-oxide layer.

3. The method of claim 1, wherein the first and second cells are formed within an array of such cells formed in parallel rows and columns formed at an angle to the rows, the method further comprising:

selectively etching the first conductive layer to form spaced apart columnar strips, each group of two adjacent strips including first and second floating gate conductor strips;

forming a second conductive layer over the face; and

etching the second conductive layer and the floating gate conductor strips to define a control gate conductor for each row that is elongate in a row direction and a plurality of floating gate conductors having edges in a row direction that are aligned with the edges in the row direction of respective control gate conductors.

4. The method of claim 3, and further comprising the steps of:

during the step of etching the second conductive layer and the floating gate conductor strips, exposing regions of the semiconductor layer;

doping the exposed regions with a dopant of a first conductivity type to form doped regions in the semiconductor layer; and

forming a thick oxide layer over the doped regions.