Flexible tester surface for testing integrated circuits

• US 4,994,735 A
• Filed: 11/14/1989
• Issued: 02/19/1991
• Est. Priority Date: 05/16/1988
• Status: Expired due to Term

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): BURNS, WILLIAM
• Application Number:
  US07/436,278
• Time in Patent Office: 462 Days
• Field of Search: 324/72.5, 324/158 P, 324/158 F, 324/158 R, 437/8, 29/847, 29/832, 357/74
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias

Abstract

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silcon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.

Claims

1. A tester surface for integrated circuits for contacting contact points of logic units on a surface of a semiconductor wafer, said tester surface comprising:

at least one layer, said layer comprising a dielectric predominantly silicon flexible material and having a thickness of no greater than fifteen microns;

a plurality of conductive vias formed in said thin flexible material; and

a thin film of patterned conductive metal deposited on said thin flexible material and in said vias to form conductive traces, including probe points for test contacting with said contact points.

2. The tester surface of claim 1, wherein said material comprises low stress silicon dioxide.

3. The tester surface of claim 1, wherein said material is comprised of low stress silicon dioxide formed by chemical vapor deposition.

4. The tester surface of claim 1, further comprising a rigid annular support fixed to the perimeter of said test surface, on the side of said test surface opposite to the side having said probe points.

5. The tester surface of claim 1, including more than one thousand probe points on the tester surface.

6. The tester surface of claim 1, wherein the probe points have a diameter of about 2 to 4 microns.

7. The tester surface of claim 6, wherein the low stress silicon dioxide has a surface stress of about 10⁵ dynes/cm².

8. The tester surface of claim 1, further comprising a second thin film of conductive metal formed overlying said thin film and insulated therefrom.

9. The tester surface of claim 1, further comprising logic circuitry connected to said probe points by said conductive traces.

10. The tester surface of claim 1, further comprising logic circuitry mounted on said tester surface and electrically connected to said conductive traces.

11. The tester surface of claim 1, further comprising integrated circuit die mounted directly on said tester surface and electrically connected to said conductive traces.

12. The tester surface of claim 10, wherein a distance between at least one of said probe points and said logic circuitry is less than two and a half inches.

13. The tester surface of claim 1, wherein the probe points have a diameter no greater than one mil.

14. The tester surface of claim 9, wherein the logic circuitry is directly connected to said probe points by said conductive traces.