Complementary semiconductor device

• US 4,994,866 A
• Filed: 01/05/1989
• Issued: 02/19/1991
• Est. Priority Date: 01/07/1988
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Awano, Yuji
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Fahmy, Wael
• Application Number:
  US07/293,527
• Time in Patent Office: 775 Days
• Field of Search: 357/16, 357/42, 357/61, 357/23.12
• US Class Current: 257/190
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

A complementary semiconductor device (CMOS gate) including a p-channel transistor (PMOS FET) and an n-channel transistor (NMOS FET). A silicon substrate, a channel layer for the p-channel transistor which comprises a first Si_1-x Ge_x layer, a Ge layer, and a second Si_1-x Ge_x layer are formed in sequence on the silicon substrate. A silicon layer, as another channel layer for the n-channel transistor, is formed on the channel layer. The ratio "x" of the first Si_1-x Ge_x layer is continuously increased from 0 to 1, and the ratio "x" of the second Si_1-x Ge_x layer is continuously decreased from 1 to 0.

Claims

1. A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising:

a silicon substrate;

a channel layer for the p-channel transistor comprising a first Si_1-x Ge_x layer, a Ge layer, and a second Si_1-x Ge_x layer formed in sequence on said silicon substrate; and

another channel layer for the n-channel transistor comprising a silicon layer formed on said channel layer.

2. A complementary semiconductor device according to claim 1, wherein the ratio "x" of said first Si_1-x Ge_x layer continuously varies from 0 to 1.

3. a complementary semiconductor device according to claim 1, wherein the ratio "x" of said second Si_1-x Ge_x layer continuously varies from 1 to 0.

4. A complementary semiconductor device according to claim 1, wherein said Ge layer consists of from 90% to 100% Ge and the rest Si.

5. A complementary semiconductor device according to claim 1, wherein said silicon substrate is i-type or p-type, said Ge layer is p-type, and said silicon layer is p-type.

6. A complementary semiconductor device according to claim 5, wherein each of said first and second SiGe layers is p-type or i-type.

7. A complementary semiconductor device according to claim 1, wherein each of said silicon substrate, said first SiGe layer, said Ge layer, said second SiGe layer, and said silicon layer is i-type.

8. A complementary semiconductor device according to claim 1, wherein:

said p-channel transistor comprises a source region and a drain region, each thereof formed by doping p-type impurities into said silicon substrate through the silicon layer and the channel layer;

said n-channel transistor comprises another source region and another drain region, each thereof formed by doping n-type impurities into said channel layer through the silicon layer; and

said device further comprises an isolation region isolating said p-channel transistor and said n-channel transistor from each other and extending to said silicon substrate through said silicon layer and said channel layer.

9. A complementary semiconductor device according to claim 8, wherein said p-channel transistor further comprises:

a gate insulating layer formed on said silicon layer between said source and drain regions of said p-channel transistor; and

source and drain electrodes respectively in contact with said source and drain regions.

10. A complementary semiconductor device according to claim 8, wherein said n-channel transistor further comprises:

a gate insulating layer formed on said silicon layer between said another source and drain regions of said n-channel transistor; and

source and drain electrodes respectively in contact with said another source and drain regions.

11. A complementary semiconductor device according to claim 1 forming a CMOS inverter gate.

12. A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising:

a silicon substrate having a main surface with a first region and a second region defined at said main surface thereof;

a channel layer for the p-channel transistor comprising a first Si_1-x Ge_x layer, a Ge layer, and a second Si_1-x Ge_x layer formed in sequence on said first and second regions;

another channel layer for the n-channel transistor comprising a silicon layer formed on said channel layer formed over said first and second regions;

a first gate insulating layer and a first gate electrode formed on said silicon layer above said first region, for the p-channel transistor; and

a second gate insulating layer and a second gate electrode formed on said silicon layer above said second region, for the n-channel transistor.