Insulated gate bipolar transistor with improved latch-up current level and safe operating area

• US 4,994,871 A
• Filed: 12/02/1988
• Issued: 02/19/1991
• Est. Priority Date: 12/02/1988
• Status: Expired due to Term

• Current Assignee: General Electric Company, Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Chang, Hsueh-Rong, Baliga, Bantval J.
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US07/279,392
• Time in Patent Office: 809 Days
• Field of Search: 357/23.4, 357/23.14, 357/34, 357/36, 357/37, 357/42, 357/43, 357/52, 357/55, 357/68, 357/86
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A UMOS IGBT has a source electrode ohmic contact area which is at least 40% base region and preferably at least 50% base region in order to provide a high latching current and a large safe operating area.

Claims

1. A UMOS IGBT comprising:

a body of semiconductor material having first and second opposed major surfaces;

said first major surface having a substantially planar plateau portion, a valley portion interspersed with said plateau portion and a pedestal wall portion connecting said plateau and valley portions, said pedestal wall portion and said plateau portion together bounding a pedestal portion of said body of semiconductor material;

a collector region of one type conductivity disposed adjacent said second major surface;

a drift region of opposite type conductivity disposed adjacent said collector region, forming a first PN junction therewith and extending to said valley portion of said first major surface;

a base region of said one type conductivity disposed in said pedestal portion of said body adjacent to said drift region, forming a second PN junction with said drift region and extending to said pedestal wall and plateau portions of said first major surface;

a source region of said opposite conductivity type, said source region being disposed in said pedestal portion of said body, forming a third PN junction with said base region and extending to said plateau and pedestal wall portions of said first major surface;

an insulated gate electrode disposed on said pedestal wall portion of said first major surface adjacent said base region and extending from said source region to said drift region for controlling the conductivity of a channel portion of said base region extending between said source and drift regions;

a collector electrode disposed on said second major surface in ohmic contact with said collector region;

a source electrode disposed on said plateau portion of said first major surface in ohmic contact with said base region and said source region; and

said base region comprising at least 40% of the area of said first major surface which is disposed in ohmic contact with said source electrode

2. The UMOS IGBT recited in claim 1 wherein:

said base region comprises at least 50% of said area of said first major surface which is disposed in ohmic contact with said source electrode.

3. The UMOS IGBT recited in claim 1 wherein:

said plateau portion of said first major surface and said pedestal portion of said body of semiconductor material each comprise a plurality of elongated, spaced apart segments.

4. The UMOS IGBT recited in claim 3 wherein:

said source region comprises a plurality of spaced apart segments.

5. The UMOS IGBT recited in claim 4 wherein:

some of said pedestal segments include a first portion which is free of source region segments and a second portion longitudinally separate therefrom which includes two source region segments.

6. The UMOS IGBT recited in claim 5 wherein:

in laterally adjacent pedestal segments a source region portion of one pedestal is laterally aligned with a source region free portion of the laterally adjacent pedestal.

7. The UMOS IGBT recited in claim 4 wherein:

said body of semiconductor material includes a plurality of first pedestal segments and a plurality of second pedestal segments;

each of said first pedestal segments is free of source region segments whereby in said first pedestal segments the entire contact area to said source electrode is base region area; and

each of said second pedestal segments includes a source region segment.

8. The UMOS IGBT recited in claim 7 wherein:

each of said second pedestal segments includes a gap in said source region whereby said base region extends to said plateau portion of said first surface and into ohmic contact with said source electrode.

9. The UMOS IGBT recited in claim 7 wherein:

in said second pedestal segments, said source region includes first and second spaced-apart segments.

10. The UMOS IGBT recited in claim 9 wherein:

each of said second pedestal segments has first and second opposed long sides and said first source region segment extends along said first long side of said pedestal and said second source region segment extends along said second long side of said pedestal.

11. The UMOS IGBT recited in claim 10 wherein:

said first and second source region segments are aligned across said pedestal; and

the portion of said base region extending to said plateau surface between said first and second source region segments includes a portion which is more heavily doped than the remainder of said base region.

12. The UMOS IGBT recited in claim 9 wherein:

said first and second source region segments are spaced apart in the direction of elongation of said pedestal.

13. The UMOS IGBT recited in claim 12 wherein:

said first and second source region segments each extend across said pedestal segment in a direction at an angle to said direction of elongation.

14. The UMOS IGBT recited in claim 7 wherein said source region includes:

an apertured source region segment disposed in one of said second pedestal segments, extending to the pedestal wall boundary of said pedestal segment along at least two sides of said pedestal segment and having at least one aperture therein which is spaced from said pedestal wall.

15. The UMOS IGBT recited in claim 14 wherein

said apertured source region segment extends to the pedestal wall boundary of said pedestal segment along the entire periphery of said pedestal segment.

16. The UMOS IGBT recited in claim 1 wherein:

said plateau portion of said first major surface has a grid configuration;

said valley portion of said first major surface comprises a plurality of spaced apart segments each disposed in alignment with an opening in the plateau portion grid; and

said pedestal wall portion of said first major surface comprises a plurality of spaced apart segments each extending between one of said valley portion segments and said plateau portion.

17. The UMOS IGBT recited in claim 16 wherein:

said source region comprises a plurality of spaced apart segments.

18. The UMOS IGBT recited in claim 17 wherein said source region includes:

an apertured source region segment, said apertured segment surrounding an opening in said plateau grid which comprises an aperture in said segment, said segment being spaced from other openings in said grid by said base region.

19. The UMOS IGBT recited in claim 18 wherein:

said apertured source region segment has only one aperture therein.

20. The UMOS IGBT recited in claim 19 wherein:

said apertured source region segment is spaced from all other openings in said grid.

21. The UMOS IGBT recited in claim 18 wherein:

said apertured source region segment has a plurality of apertures therein, each comprising an opening in said grid.

22. The UMOS IGBT recited in claim 21 wherein:

said apertured source region segment is spaced from all grid openings which do not comprise an aperture therein.

23. The UMOS IGBT recited in claim 2 wherein said source region includes:

a plurality of source region segments each of which extends across a portion of said pedestal from a first pedestal wall segment of said first major surface to a second pedestal wall segment of said first major surface.

24. A UMOS IGBT comprising:

a body of semiconductor material having first and second opposed major surfaces, said body including;

a collector region of one type conductivity disposed adjacent said second major surface;

a drift region of opposite type conductivity disposed adjacent said collector region and forming a first PN junction therewith;

a base region of said one type conductivity disposed adjacent to said drift region, forming second PN junction therewith and being spaced from said collector region by said drift region;

a source region of said opposite conductivity type forming a third PN junction with said base region and being spaced from said drift region by said base region;

said base and source regions extending to a substantially planar portion of said first major surface;

a trench structure extending into said semiconductor body from said planar portion of said first major surface whereby said first major surface includes a pedestal wall portion which bounds a pedestal structure comprise of said base and source regions;

said base region including a channel portion disposed adjacent said pedestal wall portion of said first major surface and extending between said source region and said drift region;

an insulated gate electrode disposed on said pedestal wall portion of said first major surface adjacent said channel portion of said base region and extending from said source region to said drift region for controlling the conductivity of said channel portion of said base region between said source and drift regions for carriers of said opposite conductivity type;

a source region electrode disposed on said planar portion of said first major surface in ohmic contact with said base and source regions, the area of ohmic contact between said base region and said source region electrode being no less than two-thirds of the area of the ohmic contact between said source region and said source electrode; and

a collector electrode disposed on said second major surface in ohmic contact with said collector region.

25. The UMOS IGBT recited in claim 24 wherein:

said substantially planar portion of said first major surface comprises a plurality of parallel segments which are elongated in a first direction and spaced apart in a second direction perpendicular to said first direction whereby said pedestal comprises a plurality of parallel, elongated segments.

26. The UMOS IGBT recited in claim 24 wherein:

a plurality of said pedestal segments are free of source region segments.

27. The UMOS IGBT recited in claim 24 wherein:

said substantially planar portion of said first major surface has a grid configuration; and

said pedestal structure is comprised of a plurality of grid line segments and a plurality of grid intersection segments, each grid line segment extending between and connecting two of said grid intersection segments, each grid intersection segment connecting at least three of said grid line segments.

28. The UMOS IGBT recited in claim 27 wherein said IGBT includes a plurality of pedestal grid line segments which are free of source region segments.

29. The UMOS IGBT recited in claim 25 wherein:

in each pedestal segment, a pair of elongated source region segments are disposed, each extending in said first direction, and being spaced apart from each other in said second direction whereby in traversing said pedestal segment in said second direction at a location adjacent said planar portion of said first major surface, a source region segment is encountered, then a segment of said base region is encountered and then said second source region segment is encountered.