Composite MOS transistor and application to a free-wheel diode

• US 4,994,886 A
• Filed: 08/30/1989
• Issued: 02/19/1991
• Est. Priority Date: 08/31/1988
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Nadd, Bruno
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): FAHMY, WAEL M
• Application Number:
  US07/400,855
• Time in Patent Office: 538 Days
• Field of Search: 357/41, 357/42, 357/23.4, 357/39
• US Class Current: 257/368
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H03K 17/08104 in field-effect transistor switches H03K17/0812, H03K17/0814 take precedence
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

A composite MOS transistor in a substrate of a first conductivity type comprises a gate electrode (G1), a first main electrode (A1) and a second main electrode (A2) in a substrate area (60). An auxiliary switch comprising MOS transistors (52, 53) in the substrate area, selectively provides a low impedance path between the substrate area and the lowest potential of the first and second main electrodes.

Claims

1. An integrated circuit comprising, a substrate area of a first conductivity type, a composite MOS transistor on the substrate area, the transistor including first and second main electrode regions of the second conductivity type, one of said regions selectively being at a lower potential than the other of said regions as a function of conditions of elements of the integrated circuit connected to the composite transistor, and means for connecting the region having the lowest potential at any particular time to the substrate area via a relatively low impedance path while providing a relatively high impedance path between the other region and the substrate area.

2. The circuit of claim 1 further including a voltage comparator having inputs connected to be responsive to voltages at the main electrodes of said composite transistor, the first and second main electrode regions of said composite MOS transistor being respectively connected to a first main terminal of each first and second auxiliary MOS transistors having second main terminals connected to the substrate area, said first and second auxiliary transistors having gates controlled by an output of the comparator.

3. The circuit of claim 2 wherein said main electrodes correspond to diffusions of the second conductivity type in a well of the first conductivity type, the second main terminals of said auxiliary transistors being connected to diffusions of said first conductivity type and having a high doping level, said diffusions being formed in said substrate area.

4. In combination, a substrate of a first conductivity type, a well in the substrate of a conductivity type opposite to that of the substrate, a free-wheeling monolithic diode formed in the substrate as a vertical power transistor including a composite transistor, the composite transistor including first and second main electrode regions and a substrate area of the second conductivity type, one of said regions selectively being at a lower potential than the other of said regions as a function of conditions of elements of the integrated circuit connected to the composite transistor, and means for connecting the region having the lowest potential at any particular time to the substrate via a relatively low impedance path while providing a relatively high impedance path between the other region and the substrate area, the first main electrode being connected to a source terminal of the power transistor usually connected to a first terminal of an external load, the second main electrode being connected to an access terminal for a second terminal of the load, the gate being controlled in phase opposition to the gate of the power transistor.

5. An integrated circuit comprising a substrate area having a first conductivity type, a composite MOS transistor on the substrate area, said transistor including a gate electrode responsive to a signal source, and first and second main electrode regions of a second conductivity type forming junctions with the substrate area, a single pole, double throw semiconductor switch having segments on the substrate area responsive to the voltage between the first and second main electrode regions, the substrate area forming a first terminal of the switch, the switch providing a low impedance path between the first region and the substrate area in response to the voltage of the first region being less than the voltage of the second region while providing a high impedance path between the second region and the substrate area and providing a low impedance path between the second region to the substrate area in response to the voltage of the second region being less than the voltage of the first region while providing a high impedance path between the first region and the substrate area.

6. The circuit of claim 5 wherein the switch includes second and third MOS transistors in the substrate area, and means responsive to the voltage between the first and second main electrode regions for providing a relatively low impedance source drain path for one of the second and third transistors while a source drain path of the other of the second and third transistors has a relatively high impedance in response to the voltage of the first main electrode region exceeding the voltage of the second main electrode region and vice versa in response to the voltage of the second main electrode region exceeding the voltage of the first main electrode region.

7. An integrated circuit comprising a substrate area having a first conductivity type and including first, second and third MOS transistors;

the first transistor including first and second regions having a second conductivity type contacting the substrate area and spaced from each other by a first channel in the substrate area, a first gate electrode between the first and second regions controlling the conductivity of the first channel, first and second ohmic contacts respectively on the first and second regions;

the second transistor including the first region as well as third and fourth contacting opposite conductivity type regions contacting the substrate area, the first and third regions being of the same conductivity type and spaced from each other by a second channel in the substrate area, a second gate electrode between the first and third regions controlling the conductivity of the second channel, a third ohmic contact on the third and fourth regions;

the third transistor including the second region as well as fifth and sixth contacting opposite conductivity type regions contacting the substrate area, the second and fifth regions being of the same conductivity type and spaced from each other by a third channel in the substrate area, a third gate electrode between the second and fifth regions controlling the conductivity of the third channel, a fourth ohmic contact on the fifth and sixth regions.

8. The circuit of claim 7 wherein the fourth and sixth regions have greater conductivity than the substrate area.

9. The circuit of claim 8 further including means responsive to the relative voltages at the first and second contacts for applying voltages to the second and third gate electrodes so that (a) the second and third channels have relatively low and high impedances in response to the voltage at second contact exceeding the voltage at the first contact to effectively connect the first contact to the substrate area to the exclusion of the second contact and (b) the second and third channels have relatively high and low impedances in response to the voltage at the first contact exceeding the voltage at the second contact to effectively connect the second contact to the substrate area to the exclusion of the first contact.

10. The circuit of claim 7 further including means responsive to the relative voltages at the first and second contacts for applying voltages to the second and third gate electrodes so that (a) the second and third channels have relatively low and high impedances in response to the voltage at second contact exceeding the voltage at the first contact to effectively connect the first contact to the substrate area to the exclusion of the second contact and (b) the second and third channels have relatively high and low impedances in response to the voltage at the first contact exceeding the voltage at the second contact to effectively connect the second contact to the substrate area to the exclusion of the first contact.