System and method for sharing resources of a host computer among a plurality of remote computers

• US 4,994,963 A
• Filed: 11/01/1988
• Issued: 02/19/1991
• Est. Priority Date: 11/01/1988
• Status: Expired due to Term

• Current Assignee: ICON International, Inc. (Omnicom Group Incorporated)
• Original Assignee: ICON Systems International Incorporated
• Inventors: Muhlestein, Mark, Rex, Michael E., Arthur, Ronald B., Fairclough, Dennis A., Stewart, Darryl J., Rorden, Randall J.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US07/266,381
• Time in Patent Office: 840 Days
• Field of Search: 364/200
• US Class Current: 710/305
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A system for providing a high speed digital communication path between the processor of a host computer and the processors of one or more remote computers. The high speed digital communication path allows a remote computer to efficiently share the resources of the larger host computer such as high speed magnetic disk drives and printers. A host interface located at the host computer is connected to the internal host bus of the host computer. The host interface includes a host port and components which provide for the transfer of data from the host bus to the host port. The data bits presented at the host port are arranged in a parallel format. A communication cable conveys the parallel data bits from the host port to a remote port in a remote interface at a remote computer. The remote interface provides a random access memory and components for transferring data from the remote bus to the random access memory and vice-versa. Data bits presented at the remote port are also conveyed to the random access memory. The host interface and the remote interface include control structures to supervise and arbitrate accesses to the communication cable and to the random access memory.

Claims

1. A high speed digital communication system for linking a first digital processor connected to a first bus and a second digital processor connected to a second bus, the system comprising:

first port means for presenting digital data in a parallel configuration;

first control means for conveying digital data between the first bus and the first port means;

second port means for presenting digital data in a parallel configuration;

memory means for receiving all digital data presented to the second port means destined for the first digital processor and for receiving all data presented on the first bus destined for the second digital processor;

second control means for directing flow of designated data among the second port means, the memory means, and the second bus; and

interconnecting means for establishing a parallel digital communication path between the first port means and the second port means for rapidly transferring digital data between the first bus and the second bus to permit high speed communication between the first and second digital processors.

2. A high speed digital communication system as defined in claim 1 wherein the first port means comprises:

a plurality of differential line drivers; and

a plurality of differential line receivers.

3. A high speed digital communication system as defined in claim 2 wherein the plurality of differential line drivers and differential line receivers are connected in parallel.

4. A high speed digital communication system as defined in claim 1 wherein the first port means comprises a number of differential line drivers and wherein the interconnecting means comprises a number of paired conductors, the number of differential line drivers and the number of paired conductors being at least as great as whatever maximum number of bits of digital data is to be transferred between the first digital processor and the second digital processor in a parallel configuration.

5. A high speed digital communication system as defined in claim 4 wherein the first port means comprises a plurality differential line receivers and a terminating resistance connected across each pair of conductors in the interconnecting means connected to each differential line receiver.

6. A high speed digital communication system as defined in claim 1 wherein the first port means, the second port means, and the interconnecting means each comprises a plurality of control signal paths and a parallel data transmission path of at least 16-bits in width.

7. A high speed digital communication system as defined in claim 1 wherein the interconnecting means comprises a cable having at least 16 twisted pairs of conductors.

8. A high speed digital communication system as defined in claim 7 wherein the first port means and the second port means each comprise a connector having at least 32 conductors.

9. A high speed digital communication system as defined in claim 1 wherein the first bus includes an upper and a lower byte and wherein the system further comprises means for selectively swapping the upper and lower bytes of digital data being directed to and received from the first bus.

10. A high speed digital communication system as defined in claim 9 wherein the means for swapping the upper and lower bytes comprises:

a first set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are passed straight through the first set of buffers;

a second set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are swapped while passing through the buffers; and

a control line connected to the first control means, the control line determining whether the first set or second set of buffers is active.

11. A high speed digital communication system as defined in claim 1 comprising a plurality of first port means.

12. A high speed digital communication system as defined in claim 11 further comprising means for selecting one of the plurality of first port means from an address presented on the first bus.

13. A high speed digital communication system as defined in claim 1 wherein the first bus sequentially contains an address followed by digital data destined for the address and wherein the system further comprises means for sequentially multiplexing to the first port means the address and the digital data presented on the first bus.

14. A high speed digital communication system as defined in claim 1 wherein the system further comprises means for checking for digital data transmission errors.

15. A high speed digital communication system as defined in claim 14 wherein the means for checking for digital data transmission errors comprises a parity generator circuit and a parity check circuit.

16. A high speed digital communication system as defined in claim 1 wherein the memory means comprises a dual-ported random access memory.

17. A high speed digital communication system as defined in claim 1 wherein the memory means comprises:

a random access memory;

a first buffer connected between the random access memory and the second bus in order to allow the transfer of digital data between the random access memory and the second bus; and

a second buffer connected between the random access memory and the second port means in order to allow the transfer of digital data between the random access memory and the second port means.

18. An interprocessor communication system for establishing a communication path between at least one remote processor connected to a remote bus in a remote computer and a host processor connected to a host bus in a host computer, the communication system comprising:

means for providing at least one host data port at the host computer, the host data port comprising a plurality of data transfer lines arranged in a parallel configuration;

means for establishing a digital communication path between the host bus and the means for providing at least one host data port;

means for providing a remote data port at the remote processor, the remote data port comprising a plurality of data transfer lines arranged in a parallel configuration;

means for storing digital data received from and destined for the means for providing a remote data port;

first means for transferring data between the remote bus and the means for storing;

second means for transferring data between the means for storing and the means for providing a remote data port; and

means for interconnecting the means for providing a host data port and the means for providing a remote data port to create a parallel data path therebetween and to provide for bidirectional data flow between the host bus and the remote bus for high speed exchange of digital data between the host processor and the remote processor.

19. An interprocessor communication system as defined in claim 18 wherein the means for providing a remote data port comprises:

a plurality of differential line drivers; and

a plurality of differential line receivers.

20. An interprocessor communication system as defined in claim 19 wherein the plurality of differential line drivers and the plurality of differential line receivers are connected in parallel.

21. An interprocessor communication system as defined in claim 18 wherein the means for providing a remote data port comprises a number of differential line drivers and wherein the means for interconnecting comprises a number of paired conductors, the number of differential line drivers and the number of paired conductors being at least as great as the number of bits of digital data to be transferred between the remote processor and the host processor in a parallel configuration.

22. An interprocessor communication system as defined in claim 21 wherein the means for providing at least one host port comprises a plurality of differential line receivers and a terminating resistance connected across each pair of conductors in the interconnecting means connected to each differential line receiver.

23. An interprocessor communication system as defined in claim 18 wherein the means for providing at least one host data port, the means for providing a remote data port, and the means for interconnecting each comprises a plurality of control signal paths and a parallel data transmission path of at least 16-bits in width.

24. An interprocessor communication system as defined in claim 18 wherein the means for interconnecting comprises a cable having at least 16 twisted pairs of conductors and an outer diameter of less than one-half inch.

25. An interprocessor communication system as defined in claim 24 wherein the means for providing at least one host port and the means for providing a remote port each comprise a connector having at least 32 conductors.

26. An interprocessor communication system as defined in claim 18 wherein the host bus includes an upper and a lower byte and wherein the system further comprises means for selectively swapping the upper and lower bytes of digital data being directed to and received from the host bus.

27. An interprocessor communication system as defined in claim 26 wherein the means for swapping the upper and lower bytes comprises:

a first set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are passed straight through the first set of buffers;

a second set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are swapped while passing through the buffers; and

a control line connected to the means for establishing a digital communication path, the control line determining whether the first set or second set of buffers is active.

28. An interprocessor communication system as defined in claim 18 further comprising a plurality of host data ports and means for selecting one of the plurality of host data ports from the address presented on the host bus.

29. An interprocessor communication system as defined in claim 18 wherein the host bus sequentially contains an address followed by digital data destined for the address and wherein the system further comprises means for sequentially multiplexing the address and the digital data presented on the host bus to the means for providing at least one host data port.

30. An interprocessor communication system as defined in claim 18 wherein the system further comprises means for checking for digital data transmission errors.

31. An interprocessor communication system as defined in claim 30 wherein the means for checking for data transmission errors comprises a parity generator circuit and a parity check circuit.

32. An interprocessor communication system as defined in claim 18 wherein the means for storing digital data comprises:

a random access memory;

a first buffer connected between the random access memory and the remote bus in order to allow the transfer of digital data between the random access memory and the remote bus; and

a second buffer connected between the random access memory and the remote data port in order to allow the transfer of digital data between the random access memory and the remote data port.

33. A system for allowing resources of a host computer to be shared with a remote computer, the system comprising:

remote port means at the remote computer for receiving and transmitting digital data in a parallel configuration;

memory means at the remote computer for temporarily storing digital data received from and destined to the remote port means;

remote computer control means for (a) controlling the passage of digital data between the memory means and the remote port means, and for (b) controlling passage of digital data between the memory means and an internal bus of the remote computer;

host port means at the host computer for receiving and transmitting digital data in a parallel configuration;

control means for controlling passage of digital data between the host port means and an internal bus of the host computer; and

cable means for interconnecting the remote port means and the host port means for rapidly transferring digital data between said internal bus of the host computer and said internal bus of the remote computer, the cable means bidirectionally transmitting digital data in a parallel configuration.

34. A system for exchanging digital data between internal structures of a larger host computer and a plurality of remote computers, the system comprising:

(a) a host computer interface comprising;

(i) a plurality of host ports, each of the host ports configured to transmit and receive digital data in a parallel mode;

(ii) a host address circuit for directing data contained on the bus of a host computer to said addressed host ports; and

(iii) a multiplexing circuit for sequentially passing a portion of address and digital data presented on said bus of the host computer to the host port;

(b) a remote computer interface at each remote computer, each remote computer interface comprising;

(i) a remote port configured to transmit and receive digital data in a parallel mode;

(ii) a random access memory connected to the remote port for temporary storage of the data directed to and received from the remote port; and

(iii) control and address circuits for controlling transfer of digital data between a remote bus and the random access memory by allowing data placed on said remote bus of the remote computers to address the random access memory; and

(c) a communication cable connected between said plurality of host ports and the remote port in a parallel configuration for communicating digital data presented at one of said host ports or the remote port and thereafter communicating said digital data to the other port, the communication cable comprising a plurality of pairs of conductors, each pair of conductors conveying one data bit of a byte of digital data presented at the host computer at the remote port.

35. A method for communicating digital data between a host computer and at least one remote computer, the method comprising the steps of:

conveying the digital data from a bus of the host computer to a host port, the digital data being presented in a parallel configuration at the host port;

communicating in a parallel configuration to a remote port located at the remote computer the digital data presented at the host port;

storing the digital data communicated to the remote port;

interrupting the remote computer to request access to a bus of the remote computer; and

transferring the stored digital data to the bus of the remote computer, thereby establishing a high speed communication path between the bus of the host computer and the bus of the remote computer.

36. A method as defined in claim 35 wherein the step of conveying data comprises the steps of sequentially conveying an address and conveying digital data to the host port.

37. A method as defined in claim 35 further comprising the step of swapping byte order on the host bus.

38. A method as defined in claim 35 wherein the step of communicating the data comprises the step of communicating each data bit on an individual one of a plurality of conductors.

39. A method as defined in claim 35 wherein the step of communicating the data comprises the step of differentially driving a pair of conductors for each data bit.

40. A method as defined in claim 35 wherein the step of storing the data comprises the step of entering the digital data in a random access memory.

41. A method as defined in claim 40 wherein the step of transferring the data comprises the step of transferring eight-bit bytes of data from the random access memory to said bus of the remote computer.

42. A method as defined in claim 40 further comprising the steps of:

transferring digital data presented on the bus of the remote computer to the random access memory;

presenting the digital data in the random access memory to the remote port;

communicating to the host port in a parallel configuration the digital data presented at the remote port;

interrupting the host computer to request access to the bus of the host computer; and

conveying the digital data communicated to the host port to the host bus.

43. A method as defined in claim 42 wherein the host port and the remote port are interconnected by a cable and wherein the method further comprises the step of arbitrating between the host computer and the remote computer access to the random access memory.