RAM/ROM hybrid memory architecture
First Claim
Patent Images
1. An integrated circuit memory, comprising:
- an array of memory cells arranged in rows and columns, with word lines running along rows of said array;
word line driver circuitry, connected to drive a selected one of said word lines when one of said cells in said selected row is sought to be accessed;
a sense amplification and output stage, connected to amplify the output of a selected one of said cells, and column selection circuitry, configured to connect the output of a selected one of said cells to said sense amplification and output stage;
wherein each said cell in said array includes;
a latch having first and second nodes,two pass transistors, controlled by a respective one of said word lines, and operable to connect said first and second nodes of said latch to a respective bit line pair;
and wherein at least some of said cells in said array each also include;
nonvolatile shorting elements, connected to pull one of said nodes of said latch toward a constant potential.
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Abstract
An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.
31 Citations
20 Claims
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1. An integrated circuit memory, comprising:
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an array of memory cells arranged in rows and columns, with word lines running along rows of said array; word line driver circuitry, connected to drive a selected one of said word lines when one of said cells in said selected row is sought to be accessed; a sense amplification and output stage, connected to amplify the output of a selected one of said cells, and column selection circuitry, configured to connect the output of a selected one of said cells to said sense amplification and output stage; wherein each said cell in said array includes; a latch having first and second nodes, two pass transistors, controlled by a respective one of said word lines, and operable to connect said first and second nodes of said latch to a respective bit line pair; and wherein at least some of said cells in said array each also include; nonvolatile shorting elements, connected to pull one of said nodes of said latch toward a constant potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit memory, comprising:
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an array of memory cells arranged in rows and columns, with word lines running along rows of said array; word line driver circuitry, connected to drive a selected one of said word-- lines when one of said cells in said selected row is sought to be accessed; a sense amplification and output stage, connected to amplify the output of a selected one of said cells, and column selection circuitry, configured to connect the output of a selected one of said cells to said sense amplification and output stage; wherein each said cell in said array includes; a latch having first and second nodes, two pass transistors, controlled by a respective one of said word lines, and operable to connect said first and second nodes of said latch to a respective bit-- line pair; and wherein at least some of said cells in said array each also include; a first fuse element, and a first switching transistor in series with said first fuse element, connected between said first node of said latch and a first substantially constant potential, and a second fuse element, and a second switching transistor in series with said second fuse element, connected between said second node of said latch and a second substantially constant potential. - View Dependent Claims (12, 13, 14, 15, 16)
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17. An integrated circuit memory cell, comprising:
a latch having first and second nodes, comprising a first NMOS driver transistor, having a source connected to pull down said first node, and a gate connected to said second node; a second NMOS driver transistor, having a source connected to pull down said second node, and a gate connected to said first node; first and second load elements, connected to pull up said first and second nodes respectively; two pass transistors, operable to connect said first and second nodes, repectively, to a bit-- line pair; a first fuse element, and a first switching transistor in series with said first fuse element, connected between said first node of said latch and a ground, and a second fuse element, and a second switching transistor in series with said second fuse element, connected between said second node of said latch and said ground. - View Dependent Claims (18, 19, 20)
Specification