Memory device which can function as two separate memories or a single memory

• US 4,995,005 A
• Filed: 09/26/1989
• Issued: 02/19/1991
• Est. Priority Date: 09/18/1986
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lodhi, Nusra
• Primary Examiner(s): Gossage, Glenn
• Assistant Examiner(s): Garcia, Alfonso
• Application Number:
  US07/413,507
• Time in Patent Office: 511 Days
• Field of Search: 365/189.04, 365/189.05, 365/221, 365/239, 365/230.04, 365/189.02, 365/236, 365/230.02, 365/78
• US Class Current: 365/221
• CPC Class Codes: G06F 2205/066 User-programmable number or size of buffers, i.e. number of separate buffers or their size can be allocated freely
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode, the FIFO memory device functions as two FIFO memories, one for passing data from the host CPU to the peripheral device, and one for passing data to the host CPU from the peripheral device. In another mode, the FIFO memory device functions as a single FIFO which facilitates passing data from the host CPU to the peripheral device or from the peripheral device to the host CPU. The FIFO incloudes two RAMs addressed by a set of address counters. Of importance, the host CPU can bypass the address counters to directly address each RAM, thereby reading data from or writing data into either RAM regardless of the state of the address counters.

Claims

1. A memory device comprising:

first data storage means having n locations for storing n words of data, where n is an integer greater than one;

second data storage means having m locations for storing m words of data, where m is an integer greater than one; and

control means for functioning in one of a first mode and a second mode, said control means receiving a first set of words of data and storing said first set of words of data in sequential locations within said first data storage means when said control means is in said first mode, said control means receiving a second set of words of data and storing said second set of words of data in sequential locations within said second data storage means when said control means is in said first mode, said control means providing data stored in said sequential locations within said first and second data storage means, thereby causing said first and second data storage means to function as an n location FIFO memory and an m location FIFO memory, respectively, when said control means is in said first mode, said control means storing a third set of words of data in sequential locations within said first data storage means and then storing words of data within said third set in sequential locations within said second data storage means after storing data in the last location in said first data storage means when said control means is in said second mode, said control means providing data stored in sequential locations within said first data storage means and then providing data stored in sequential locations within said second data storage means after providing data stored in the last location of said first data storage means when said control means is in said second mode, thereby causing said first and second data storage means to function as a single n+m location FIFO memory.

2. The memory device of claim 1 wherein said first data storage means is a first RAM and said second data storage means is a second RAM, and said control means comprises:

a first counter for providing sequential addresses to said first RAM;

a first data bus for providing data to said first RAM, said control means storing data from said first data bus in locations within said first RAM selected by said first counter;

a second data bus; and

a second counter for providing sequential addresses to said second RAM, said control means storing data from said second data bus in locations within said second RAM selected by said second counter when said control means is in said first mode, said control means storing data from said first data bus in locations within said second RAM selected by said second counter after data from said first data bus is stored in the last location of said first RAM when said control means is in said second mode.

3. The memory device of claim 2 further comprising:

a third counter for providing sequential addresses to said first RAM, said control means providing data stored in locations within said first RAM selected by said third counter on said second data bus; and

a fourth counter for providing sequential addresses to said second RAM, said control means providing data stored in locations within said second RAM selected by said fourth counter on said first data bus when said control means is in said first mode, said control means providing data stored in locations within said second RAM selected by said fourth counter on said second data bus after data from the last location in said first RAM is provided on said second data bus when said control means is in said second mode.

4. The memory device of claim 3 further comprising:

a first port coupled to said first data bus for receiving data from and providing data to a first device;

a second port coupled to said second data bus for receiving data from and providing data to a second device, whereby when said control means is in said first mode, said memory device receives said first set of words of data from said first device and provides said first set of words of data on a first-in-first-out basis to said second device when said control means is in said first mode, said memory device receiving said second set of words of data from said second device and providing said second set of words of data to said first device when said control means is in said first mode, said memory device receiving said third set of words of data from said first device and providing said third set of words of data to said second device on a first-in-first-out basis when said control means is in said second mode.

5. The memory device of claim 4 further comprising means for receiving an address from said first device, said memory device providing data from a location within said first or second RAM, said location being determined by said received address, said memory device also storing data from said first device in a location within said first or second RAM, said location being determined by said received address, so that said first device can receive data from or store data in a desired location within said first and second RAMs regardless of the contents of said first, second, third and fourth counters.

6. The memory device of claim 4 further comprising:

a first flag register for receiving data from said first device, said memory device selectively providing a first signal to said first device when the contents of said first counter equal the contents of said first flag register;

a first end of count register for selectively providing a first end of count signal to said first device when the contents of said first end of count register equal the contents of said first counter; and

wherein said first counter can be preset to an initial value selected by said first device, thereby permitting said memory device to load a predetermined block of locations within said first RAM with data from said first device.

7. The memory device of claim 6 further comprising:

second, third and fourth flag registers for receiving data from said first device, said memory device selectively providing second, third, and fourth output signals when the contents of said second, third and fourth counters equal the contents of said second, third and fourth flag registers, respectively; and

second, third and fourth end of count registers for receiving data from said first device, said memory device providing second, third, and fourth end of count signals when the contents of said second, third and fourth counters equal the contents of said second, third and fourth end of count registers, respectively,

and wherein said second, third, and fourth counters can be preset to initial values selected by said first device.

8. A memory device comprising:

first data storage means having n locations for storing n words of data, where n is an integer greater than one;

second data storage means having m locations for storing m words of data, where m is an integer greater than one; and

control means for functioning in one of a first mode and a second mode, said control means receiving a first set of words of data and storing said first set of words of data in sequential locations within said first data storage means when said control means is in said first mode, said control means receiving a second set of words of data and storing said second set of words of data in sequential locations within said second data storage means when said control means is in said first mode, said control means providing data stored in said sequential locations within said first and second data storage means, thereby causing said first and second data storage means to function as an n location last-in-first-out memory and an m location last-in-first-out memory, respectively, when said control means is in said first mode, said control means storing a third set of words of data in sequential locations within said first data storage means and then storing words of data within said third set in sequential locations within said second data storage means after storing data in the last location in said first data storage means when said control means is in said second mode, said control means providing data stored in sequential locations within said first and second data storage means on a last-in-first-out basis when said control means is in said second mode, thereby causing said first and second data storage means to function as a single n+m location last-in-first-out memory.