Method of manufacture interconnect device

• US 4,995,941 A
• Filed: 05/15/1989
• Issued: 02/26/1991
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: World Properties Incorporated
• Original Assignee: Rogers Corporation (Rogers Communications Inc.)
• Inventors: Nogavich, Eugene, Lebow, Sanford, Nelson, Gregory H.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US07/352,112
• Time in Patent Office: 652 Days
• Field of Search: 156/629, 156/247, 156/630, 156/633, 156/272.8, 156/634, 156/289, 156/643, 156/644, 156/645, 156/652, 156/655, 156/656, 156/659.1, 156/664, 156/665, 156/666, 156/668 , 156/901, 156/902, 29/827, 29/846, 29/852, 29/874, 430/313, 430/314, 174/68.5, 361/406, 361/421, 427/96, 427/97, 437/220, 437/182, 437/228, 219/121.68, 219/121.69, 219/121.7, 219/121.71, 219/121.85, 357/69, 357/70, 428/596, 428/601, 428/131, 428/209, 428/901
• US Class Current: 216/18
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09918 Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
• CPC Class Codes: H05K 2203/0152 Temporary metallic carrier, e.g. for transferring material
• CPC Class Codes: H05K 2203/0726 Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
• CPC Class Codes: H05K 3/0035 of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/205 using a pattern electroplated or electroformed on a metallic carrier
• CPC Class Codes: H05K 3/386 by the use of an organic polymeric bonding layer, e.g. adhesive
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4652 Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4655 by using a laminate characterized by the insulating layer general-purpose insulating materials H05K1/03, H05K3/4673
• CPC Class Codes: H05K 3/4673 Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer similar methods for protective coatings H05K3/28
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 29/49121 Beam lead frame or beam lead device
• CPC Class Codes: Y10T 428/24273 : including aperture
• CPC Class Codes: Y10T 428/24917 : including metal layer

Abstract

An interconnect device for electronic components, such as integrated circuits, multichip modules and the like, and the method of manufacture thereof are presented. The interconnect device has two layers of circuitry, one for signal transmission and one for voltage plane. The interconnect device is made by a processing on a stainless steel carrier plate to achieve high lead count capability with fine line widths and spacing, as well as precise registration layer to layer. Laser drilling is used to define interconnect vias between signal and voltage (power or ground) plane layers.

Claims

1. A method of making an interconnect drive for electronic components comprising the steps of:

forming a release layer on a carrier plate;

forming a conductive pattern of leads on said release layer;

forming registration features on said release layer;

bonding a laminate to said conductive pattern of leads by a layer of adhesive, said laminate including a conductive sheet and a dielectric sheet wherein said dielectric sheet faces said conductive pattern of leads and said conductive sheet faces away from said adhesive layer;

forming via holes in said laminate in a predetermined pattern, said via holes extending through said conductive sheet, dielectric sheet and adhesive layer to expose said leads;

depositing conductive material in said via holes and onto said conductive sheet of said laminate to interconnect said leads to said conductive sheet;

forming at least one window in said device by removing selected parts of said conductive material, said laminate and said adhesive layer, said window extending through said dielectric sheet and adhesive layer to expose said leads; and

forming at least one frame spaced from and surrounding said window in said device by removing selected parts of said conductive material, said laminate and said adhesive layer, said frame extending through said dielectric sheet and adhesive layer to expose said leads.

2. The method of claim 1 wherein:

said carrier plate comprises stainless steel.

3. The method of claim 1 wherein:

said release layer comprises at least one layer of metal plated on a front surface of said carrier plate.

4. The method of claim 3 wherein said carrier plate includes sides and a back surface and wherein:

said release layer is wrapped around said sides and extends along a portion of said back surface.

5. The method of claim 3 wherein said release layer comprises:

a first layer of nickel electroplated to said carrier plate; and

a second layer of copper electroplated to said first layer of nickel.

6. The method of claim 1 wherein said step of forming said conductive pattern of leads comprises the steps of:

depositing a layer of resist material on said release layer;

removing parts of said release layer at locations where said leads are to be formed;

forming a pattern of resist material on said release layer;

depositing conductive material on said release layer to form said leads at said locations; and

removing the remainder of resist material.

7. The method of claim 6 wherein said step of depositing said conductive material to form said leads comprises the step of:

electroplating a first layer of gold, tin or nickel;

electroplating a second layer of copper on said first layer; and

electroplating a third layer of gold, tin or nickel on said second layer.

8. The method of claim 1 wherein:

said adhesive layer is activated by heat and pressure.

9. The method of claim 1 including the step of:

pre-punching registration holes in said adhesive layer and laminate for alignment with said registration features on said release layer.

10. The method of claim 1 wherein said step of forming via holes comprises:

forming a pattern of resist material on said conductive layer;

removing resist material at locations at which vias are to be formed;

etching said conductive layer at said locations to remove material from said conductive layer and define a mask of said conductive layer with openings therein.

11. The method of claim 1 wherein said step of forming said via holes comprises:

laser etching through said dielectric sheet and said adhesive layer using said conductive sheet as a mask to laser etch at said openings.

12. The method of claim 1 wherein said step of depositing conductive material in said via holes comprises:

electroless depositing a first conductive layer in said via holes; and

electroplating a second conductive layer on said first conductive layer.

13. The method of claim 12 wherein said electroplated second conductive layer covers said conductive sheet of said laminate and wherein said steps of forming said window and frame include the step of:

removing corresponding second and third portions of said electroplated second conductive layer at the locations of said window and frame.

14. The method of claim 13 wherein said steps of forming said window and frame comprise:

laser etching through said dielectric sheet and said adhesive layer using said electroplated second conductive layer as a mask.

15. The method of claim 1 including:

depositing protective material in said window and frame.

16. The method of claim 1 including:

removing said carrier plate and release layer from said conductive pattern of leads.

17. The method of claim 16 wherein said release layer comprises electroplated metal and wherein said step of removing said release layer includes:

etching said electroplated metal.

18. An interconnect device for electronic components formed by the process of claim 1.

19. The method of claim 1 wherein said step of bonding a laminate to said conductive pattern of leads includes:

positioning an adhesive between said dielectric sheet and said conductive pattern of leads.