×

Carrier stability erasure filling system for communications over electricity distribution network

  • US 4,996,513 A
  • Filed: 02/20/1990
  • Issued: 02/26/1991
  • Est. Priority Date: 02/20/1990
  • Status: Expired due to Term
First Claim
Patent Images

1. In a communication system using the current waveform of an electricity distribution network as a carrier a signal being present as composite binary digits, each composite binary digit being defined by a pulse pattern at preselected positions on the voltage waveform, the pulses being spaced along the waveform so that they are ordered in time, the pulse pattern for a binary "1" being complementary to the pulse pattern for a binary "0", a system for identifying said binary digits comprising:

  • sampling the current waveform at the preselected positions to obtain an ordered set of waveform values, the magnitudes of the values corresponding to a binary digit pulse pattern being larger, in a noise-free system, when the binary digit corresponding to that pulse pattern is present than when it is absent;

    examining the ordered waveform values for each bit to determine if the values fall within preset criteria indicative of a stable carrier;

    when the ordered waveform values for a particular bit all fall within the preset criteria, identifying that particular bit as having the binary value corresponding to its sampled pulse pattern;

    when at least some of the ordered waveform values for a particular bit fall outside the preset criteria, labelling that particular bit as suspect;

    for each suspect bit, testing the ordered values of that bit and of adjacent bits to determine whether a series of a first predetermined number of successive values meets the preset stability criteria, said series including at least a second predetermined number of successive values from the suspect bit and at least the second predetermined number of successive values from an adjacent bit; and

    identifying the binary value, if any, of the suspect bit based upon said second predetermined number of successive values from the suspect bit when the test of the testing step is met, otherwise labelling the suspect bit as uncorrectable.

View all claims
  • 8 Assignments
Timeline View
Assignment View
    ×
    ×