Integrated semiconductor chip package

• US 4,996,587 A
• Filed: 03/23/1990
• Issued: 02/26/1991
• Est. Priority Date: 04/10/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hinrichsmeyer, Kurt, Kelley, Gordon A. Jr., Straehle, Werner, Noth, Richard W.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Whitehead, Jr., Carl
• Application Number:
  US07/498,134
• Time in Patent Office: 340 Days
• Field of Search: 357/74, 357/70, 357/69, 357/71
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A semiconductor package utilizing a carrier with substantially parallel top and bottom surfaces having a recess in the bottom surface and a slot in the top surface communicating with the recess in the bottom surface and provided with electrical conductors on its top surface is provided with an integrated semiconductor chip having a major surface and contact pads on the major surface in the recess of the carrier, with said contact pads positioned in the region of said slot so that the contact pads can be connected by lead wires passing through said slot, to the conductors on the top side of the carrier. The active surface of the chip containing the contact pads is encapsulated but the back surface of the chip and carrier is left exposed to improve the thermal characteristics of the chip while maintaining a low package profile.

Claims

1. A semiconductor package comprising:

a chip carrier with substantially parallel top and bottom surfaces,

a recess in the bottom surface,

at least one slot in the top surface substantially smaller than said recess communicating with the recess in the bottom surface,

electrical conductors arranged at least on the top surface of said carrier,

in integrated semiconductor chip having a major surface and contact pads on said major surface arranged in the recess of said carrier with said contact pads positioned in the region of said slot, and

lead wires passing through said lot in connecting the contact pads on the chip to the conductors on the top side of the carrier.

2. The package of claim 1 wherein the backside of the chip and the bottom surface of the carrier lie in the same plane.

3. The package of claim 2 wherein the slot edges are beveled.

4. The package of claim 3 wherein the carrier with the embedded chip has a thickness of 0.8 to 1.2 millimeters and the thickness of the carrier in the region of the recess is 0.2 to 0.5 millimeters.

5. The package as claimed in claim 4 wherein the carrier is made of reinforced polyimide.

6. The package of claim 4 wherein the carrier is made of ceramic material.

7. The package of claim 4 wherein passive and active components are arranged on the carrier top surface.

8. A stack of packages wherein each package comprises

a chip carrier with substantially parallel top and bottom surfaces,

a recess in the bottom surface,

at least one slot in the top surface substantially smaller than said recess communicating with the recess in the bottom surface,

electrical conductors arranged at least on the top surface of said carrier,

an integrated semiconductor chip having a major surface and contact pads on said major surface arranged in the recess of said carrier with said contact pads positioned in the region of said slot, and

lead wires passing through said slot in connecting the contact pads on the chip to the conductors on the top side of the carrier.

9. A semiconductor package comprising:

a chip carrier with substantially parallel top and bottom surfaces,

at least two recesses in the bottom surface,

at least two slots in the top surface of said carrier, each slot communicating with a respective recess in the bottom surface,

electrical conductors arranged on the top surface of said carrier,

an integrated semiconductor chip having a major surface and contact pads on said major surface arranged in each recess in said carrier, the contact pads of the respective chip in the recess positioned in the region of the slot communicating with the recess,

lead wires passing through each said slot and connecting the contact pads on each said chip to the conductors on the top side of the carrier.