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Syndrome sequential decoder

  • US 4,998,253 A
  • Filed: 03/08/1989
  • Issued: 03/05/1991
  • Est. Priority Date: 03/11/1988
  • Status: Expired due to Term
First Claim
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1. A syndrome sequential decoding system for decoding a received code word sequence which is convolutionally encoded, comprising:

  • an input terminal for receiving the received code word sequence which is convolutionally encoded, said received code word sequence including an information bit and a parity bit;

    an input/output buffer memory for storing data representing said received code word sequence;

    a syndrome former means coupled to receive said received code word sequence from said input terminal, for generating a syndrome sequence which is a product of the received code word sequence and a parity check matrix of said convolutional code;

    an estimated error buffer memory for indicating an estimated channel error sequence;

    a syndrome buffer memory coupled with the output of said syndrome former means, for storing said output of said syndrome former means;

    a syndrome register coupled to said syndrome buffer memory for storing data representing a new syndrome state;

    shifting means for receiving bits from said syndrome buffer memory and storing said bits in said syndrome register, said shifting means including a decoding pointer which is shiftable to indicate one of a plurality of syndromes in said syndrome buffer memory;

    a comparator means coupled with the output of said syndrome register for testing whether or not the contents of said syndrome register are all zero;

    an algorithm controller coupled to receive the output of said comparator means for determining, in event of detection of an error, a position of an error bit and for producing a signal indicative of said position of said error bit, said algorithm controller being coupled to said estimated error buffer memory for inverting a bit located at said position of said error bit in said estimated error buffer memory in the event of detection of an error;

    a back search limit pointer which is shiftable to specify one of a plurality of different bit positions in said estimated error buffer memory, for restricting said decoding pointer so that it does not go beyond a bit position specified by said back search limit pointer;

    an exclusive-OR circuit coupled to receive the output of said input/output buffer memory and the output of said estimated error buffer memory for inverting an output bit of the output of said input/output buffer memory depending upon the output of said estimated error buffer memory; and

    an output terminal coupled to an output of said exclusive-OR circuit for supplying an error corrected decoded output sequence.

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