Avalanche breakdown semiconductor device

• US 4,999,683 A
• Filed: 12/28/1989
• Issued: 03/12/1991
• Est. Priority Date: 12/30/1988
• Status: Expired due to Term

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Suzuki, Tohru, Terashima, Takayoshi, Kiyomura, Akio
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): NGO, NGAN V
• Application Number:
  US07/458,398
• Time in Patent Office: 439 Days
• Field of Search: 357/13, 357/20, 357/30 A, 357/38, 357/49, 357/52
• US Class Current: 257/606
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

A Zener diode comprising a semiconductor substrate having an n-type region partly exposed at a main force of the substrate, a p⁺ -type region disposed contiguous to the n-type region and exposed at the main face of the semiconductor substrate, and an n⁺ -type region also exposed at the main face of the substrate and contiguously surrounded by the p⁺ -type region besides being contiguous to the p⁺ -type region. The arrangement of the semiconductor regions in relation to one another, and an an insulating layer on the main face of the substrate and to a pair of electrodes thereon, is such that the breakdown voltage is free from the influence of temperatures and of the ions contained in the insulating layer.

Claims

1. An avalanche breakdown semiconductor device comprising:

(a) a semiconductor substrate [42] having a main face [44] and comprising;

(1) a first region [56] of a first conductivity type partly exposed at the main face of the semiconductor substrate;

(2) a second region [60] of a second conductivity type, opposite to the first conductivity type, exposed at the main face of the semiconductor substrate and disposed contiguous to the first region; and

(3) at least one third region [62] of the first conductivity type exposed at the main face of the semiconductor substrate and disposed contiguous to both the first and second regions so that the second and third regions provide therebetween a pn junction which is exposed at the main face of the semiconductor substrate, the third region being surrounded by the second region, as seen at the main face of the semiconductor substrate, and being higher in impurity concentration than the first region;

(b) an insulating layer [46] formed on the main face of the semiconductor substrate so as to cover the pn junction between the second and third regions and substantially all the surface of the third region exposed at the main face of the semiconductor substrate;

(c) a first electrode [48] formed on the main surface of the insulating layer so as to cover substantially all the exposed surface of the third region of the semiconductor substrate via the insulating layer and electrically connected to the second region of the semiconductor substrate; and

(d) a second electrode [52] formed on the face opposite to the main face of the semiconductor substrate and electrically connected to the first region thereof.

2. The avalanche breakdown semiconductor device of claim 1 wherein the semiconductor substrate further comprises a fourth region [58] of the first conductivity type disposed contiguous to the first region [56] and being higher in impurity concentration than the first region, the second electrode being electrically connected to the first region via the fourth region.

3. The avalanche breakdown semiconductor device of claim 1 wherein the third region of the semiconductor substrate comprises:

(a) a first subregion [62] contiguously surrounded by the second region [60]; and

(b) a second subregion [80] contiguously surrounded by the first subregion and extending into the semiconductor substrate deeper from the main face thereof than the first subregion.

4. The avalanche breakdown semiconductor device of claim 3 wherein the second subregion [80] of the third region of the semiconductor substrate is higher in impurity concentration than the first subregion [62] thereof.

5. The avalanche breakdown semiconductor device of claim 3 wherein the semiconductor substrate further comprises a fourth region [58] of the first conductivity type disposed contiguous to the first region [56] and to the second subregion [80] of the third region and being higher in impurity concentration than the first region, the second electrode being electrically connected to the first region via the fourth region.

6. The avalanche breakdown semiconductor device of claim 1 wherein the second region [60] extends deeper into the semiconductor substrate from the main face thereof than does the third region [62].

7. The avalanche breakdown semiconductor device of claim 1 wherein the semiconductor substrate further comprises a fourth region [58c] of the second conductivity type disposed contiguous to the first region [56], the second electrode being electrically connected to the first region via the fourth region.

8. The avalanche breakdown semiconductor device of claim 1 wherein, as seen at the main face of the semiconductor substrate, the third region [62] of the semiconductor substrate is circular in shape and is concentrically surrounded by the second region [60] of annular shape.

9. The avalanche breakdown semiconductor device of claim 1 wherein, as seen at the main face of the semiconductor substrate, the third region [62] of the semiconductor substrate is annular in shape, concentrically surrounded by the second region [60] of annular shape and concentrically surrounding another second region [122].

10. An avalanche breakdown semiconductor device comprising:

(a) a semiconductor substrate having a main face and comprising;

(1) a first region [98] of a first conductivity type partly exposed at the main face of the semiconductor substrate;

(2) a second region [100] of a second conductivity type, opposite to the first conductivity type, exposed at the main face of the semiconductor substrate and disposed contiguous to the first region;

(3) a third region [104] of the first conductivity type exposed at the main face of the semiconductor substrate and disposed contiguous to both the first and second regions so that the second and third regions provide therebetween a pn junction which is exposed at the main face of the semiconductor substrate the third region being surrounded by the second region, as seen at the main face of the semiconductor substrate, and being higher in impurity concentration than the first region;

(4) a fourth region [96] of the second conductivity type disposed contiguous to the first region; and

(5) a fifth region [102] of the first conductivity type contiguously surrounded by the second region and exposed at the main face of the semiconductor substrate;

(b) an insulating layer [46] formed on the main face of the semiconductor substrate so as to cover the pn junction between the second and third regions and substantially all the surface of the third region exposed at the main face of the semiconductor substrate;

(c) a first main electrode [108] electrically connected to the fifth region o the semiconductor substrate;

(d) a second electrode [106] electrically connected to the fourth region of the semiconductor substrate; and

(e) a gate electrode [110] formed on the surface of the insulating layer so as to cover substantially all the exposed surface of the third region of the semiconductor substrate and electrically connected to the second region of the semiconductor substrate.

11. An avalanche breakdown semiconductor device comprising:

(a) a semiconductor substrate [42a] having a main face [44] and comprising;

(1) a first region [56] of a first conductivity type partly exposed at the main face of the semiconductor substrate;

(2) a second region [60] of a second conductivity type, opposite to the first conductivity type, exposed at the main face of the semiconductor substrate and disposed contiguous to the first region; and

(3) at least one third region of the first conductivity type exposed at the main face of the semiconductor substrate and disposed contiguous to both the first and second regions so that the second and third regions provide therebetween a pn junction which is exposed at the main face of the semiconductor substrate, the third region being surrounded by the second region, as seen at the main face of the semiconductor substrate, and being higher in impurity concentration than the first region, the third region comprising a first subregion [62] contiguously surrounded by the second region [60] and a second subregion [80] contiguously surrounded by the first subregion and being higher in impurity concentration that the first subregion [62] thereof;

(b) an insulating layer [46] formed on the main face of the semiconductor substrate so as to cover the pn junction between the second and third regions and substantially all the surface of the third region exposed at the main face of the semiconductor substrate;

(c) a first electrode [48]]formed on the surface of the insulating layer so as to cover substantially all the exposed surface of the first subregion [62] and electrically connected to the second region of the semiconductor substrate; and

(d) a second electrode [52] formed on the face opposite the main face of the semiconductor substrate and electrically connected to the first region thereof.