Nonvolatile semiconductor memory having a stress test circuit

• US 4,999,813 A
• Filed: 04/20/1989
• Issued: 03/12/1991
• Est. Priority Date: 10/28/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Miyamoto, Junichi, Atsumi, Shigeru, Ohtsuka, Nobuaki
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/341,287
• Time in Patent Office: 691 Days
• Field of Search: 365/104, 365/184, 365/185, 365/189.06, 365/189.09, 365/201, 365/189.11, 365/204, 371/21.01, 371/21.4
• US Class Current: 365/185.18
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

In a nonvolatile semiconductor memory, a plurality of nonvolatile semiconductor memory cells are arranged in a matrix form. Each of the memory cells is connected to a corresponding one of a plurality of bit lines and to a corresponding one of a plurality of word lines. The ends of the bit lines are commonly connected to a programming transistor for setting a programming mode through transistors for selecting the bit lines. The transistors are connected to column decoders and the word lines are connected to a row decoder. Furthermore, the other ends of the bit lines are connected to a common connecting line through transistors for setting a test mode and the common connecting line is connected to a node between the test mode transistors and a series circuit of a transistor and a dummy memory cell in a clamp circuit. The transistor of the clamp circuit is connected to a high voltage and the series circuit is connected to the ground. In the test mode, the programming transistor and the bit line selecting transistors are turned off and the test mode transistors and the transistor connected to the clamp circuit are turned on. Thus, a test voltage is applied to the memory cells through the common connecting line, the test mode transistors and the bit lines.

Claims

1. A nonvolatile semiconductor memory comprising:

a plurality of bit lines each having a first end an a second end;

a plurality of word lines;

nonvolatile semiconductor memory cells arranged in a matrix form and respectively connected to corresponding ones of said bit lines and word lines;

means for selecting one of said bit lines and one of said word lines;

a first transistor coupled to the first end of each of said bit lines, said first transistor being turned on in a data programming mode of the semiconductor memory;

a plurality of second transistors respectively connected between the second ends of the bit lines and a common connecting line, said first transistor being turned off and said second transistors being turned on in a test mode of the semiconductor memory, each of said second transistors having a mutual conductance smaller than that of said first transistor; and

means connected to said common connecting line for applying a stress voltage to said bit lines in the test mode.

2. A nonvolatile semiconductor memory according to claim 1, further comprising switching means connected between said common connecting line and a ground potential, said switching means being turned on in response to a reset signal, and wherein said second transistors are turned on in response to the reset signal, and said bit lines are grounded via said second transistors, said common connecting line and said switching means, and thus are reset.

3. A nonvolatile semiconductor memory according to claim 1, wherein a programming voltage is applied to said bit lines via said first transistor in the programming mode.

4. A nonvolatile semiconductor memory according to claim 3, wherein said means for applying the stress voltage to said common connecting line includes stress voltage application means for converting the programming voltage into a stress voltage and then applying the stress voltage to said common connecting line in the test mode.

5. A nonvolatile semiconductor memory according to claim 3, wherein

said stress voltage application means includes a third transistor which is connected to receive the programming voltage and is turned on in the test mode, a fourth transistor which is connected in series with said third transistor and which is turned on in the test mode, and a dummy memory cell having substantially the same construction as one of said memory cells, connected between said fourth transistor, and a ground potential;

and

said common connecting line is connected to a connection node between said third and fourth transistors.

6. A nonvolatile semiconductor memory according to claim 4, further comprising switching means connected between said common connecting line and a ground potential, said switching means being turned on in response to a reset signal, and wherein said second transistors are turned on in response to the reset signal, and said bit lines are grounded via said second transistors, said common connecting line and said switching means, and thus are reset.

7. A nonvolatile semiconductor memory according to claim 6, further comprising:

first converting means for converting a test signal into a first high voltage test signal of a high voltage level; and

second converting means for converting the test signal into a second high voltage test signal of the high voltage level

wherein said stress voltage application means is energized in response to the first high voltage test signal, and said second transistors are turned on in response to the second high voltage test signal or the reset signal.

8. A nonvolatile semiconductor memory according to claim 7, wherein the voltage level of said first high voltage test signal is the programming voltage.

9. A nonvolatile semiconductor memory according to claim 4, wherein said second transistors are turned on in response to a test signal in the test mode.

10. A nonvolatile semiconductor memory according to claim 9, which further comprises converting means for converting the test signal into a high voltage test signal of a high voltage level and in which said stress voltage application means is energized and said second transistors are turned on in response to the high voltage test signal.

11. A nonvolatile semiconductor memory according to claim 10, wherein

said stress voltage application means includes a third transistor which is connected to receive the programming voltage and is turned on in the test mode, a fourth transistor which is connected in series with said third transistor and which is turned on in the test mode, and a dummy memory cell having substantially the same construction as one of said memory cells, connected between said fourth transistor and a ground potential;

and

said common connecting line is connected to a connection node between said third and fourth transistors.

12. A nonvolatile semiconductor memory according to claim 10, wherein the high voltage level of said high voltage test signal is the programming voltage.