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Nonvolatile semiconductor memory having a stress test circuit

  • US 4,999,813 A
  • Filed: 04/20/1989
  • Issued: 03/12/1991
  • Est. Priority Date: 10/28/1987
  • Status: Expired due to Term
First Claim
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1. A nonvolatile semiconductor memory comprising:

  • a plurality of bit lines each having a first end an a second end;

    a plurality of word lines;

    nonvolatile semiconductor memory cells arranged in a matrix form and respectively connected to corresponding ones of said bit lines and word lines;

    means for selecting one of said bit lines and one of said word lines;

    a first transistor coupled to the first end of each of said bit lines, said first transistor being turned on in a data programming mode of the semiconductor memory;

    a plurality of second transistors respectively connected between the second ends of the bit lines and a common connecting line, said first transistor being turned off and said second transistors being turned on in a test mode of the semiconductor memory, each of said second transistors having a mutual conductance smaller than that of said first transistor; and

    means connected to said common connecting line for applying a stress voltage to said bit lines in the test mode.

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