Method for producing a monolithically integrated optoelectronic device

• US 5,001,080 A
• Filed: 10/26/1987
• Issued: 03/19/1991
• Est. Priority Date: 05/18/1984
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Miura, Shuichi, Sakurai, Teruo, Yamakoshi, Shigenobu, Machida, Hideki, Wada, Osamu, Sanada, Tatsuyuki
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Bunch, William
• Application Number:
  US07/112,305
• Time in Patent Office: 1,240 Days
• Field of Search: 148/DIG. 8, 148/51, 148/102, 148/111, 148/65, 148/131, 148/135, 148/161, 148/168, 148/169, 156/610-615, 156/643, 156/647, 156/659.1, 156/661.1, 156/662, 437/40, 437/39, 437/51, 437/54, 437/59, 437/81, 437/90, 437/107, 437/129, 437/127, 437/228, 437/229, 437/904, 437/905, 437/912, 437/962, 437/974, 437/981, 437/947, 437/133, 437/17 6, 357/41, 357/15, 357/17
• US Class Current: 438/23
• CPC Class Codes: H01L 21/2633 for etching, e.g. sputteretching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01S 5/0261 Non-optical elements, e.g. laser driver components, heaters H01S5/0265 takes precedence
• CPC Class Codes: Y10S 148/051 Etching
• CPC Class Codes: Y10S 148/111 Narrow masking
• CPC Class Codes: Y10S 148/161 Tapered edges
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope facing the first gentle slope; an optical semiconductor element is constructed using the single crystalline layer. An electronic semiconductor element is constructed using the substrate surface. A wiring layer connects electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slopes.

Claims

1. A process for producing a semiconductor device, comprising the steps of:

forming a low substrate surface in a substrate with a gentle slope from the substrate surface;

forming on the low substrate surface a single crystalline layer substantially level with the substrate surface;

forming an optical semiconductor element and an electronic semiconductor element using the single crystalline layer and the substrate surface, respectively; and

forming a wiring layer connecting the optical semiconductor element and the electronic semiconductor element on the gentle slope;

wherein said gentle slope is formed on said substrate by the steps of;

forming a first resist layer on said substrate in a stripe form;

subjecting the stripe-shaped resist layer to heat-treatment so that the edges of the stripe-shaped resist layer are rounded;

covering the substrate and stripe-shaped resist layer on regions other than where the gentle slope is to be formed at one side; and

etching the exposed substrate by ion beam etching.

2. A method according to claim 1, wherein said gentle slope is formed on said substrate by a method comprising the steps of:

forming a polyimide resin multilayer obtained by forming a first polyimide resin layer heat-treated at a temperature on the substrate, a second polyimide resin layer heat-treated at a second temperature lower than the first temperature, and so on;

patterning the polyimide resin multilayer through a mask to make a recess having a gentle slope; and

patterning the substrate by a dry-etching process.

3. A method according to claim 1, wherein said dry-etching is ion beam etching or reactive ion etching.

4. A method for producing a semiconductor device comprising the steps of:

forming a substrate;

forming a low substrate surface in the substrate surface with a first gentle slope from the substrate surface;

forming on the low substrate surface a single crystalline layer nearly level with the substrate surface;

forming in the single crystalline layer a second gentle slope facing the first gentle slope;

forming an optical semiconductor element using the single crystalline layer;

forming an electronic semiconductor element using the substrate surface; and

forming a wiring layer connecting electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slope;

wherein said gentle slope is formed on said substrate by a method comprising the steps of;

forming a first resist layer on said substrate in a stripe form;

subjecting the stripe shaped resist layer to heattreatment so that the edges of the stripe shaped resist layer are rounded;

covering the substrate and stripe-shaped resist layer on regions other than where the gentle slope is to be formed; and

etching the exposed substrate by ion beam etching.

5. A process for producing a semiconductor device, comprising the steps of:

forming a low substrate surface in a substrate with a gentle slope from the substrate surface;

forming on the low substrate surface a single crystalline layer substantially level with the substrate surface;

forming an optical semiconductor element and an electronic semiconductor element using the single crystalline layer and the substrate surface, respectively; and

forming a wiring layer connecting the optical semiconductor element and the electronic semiconductor element on the gentle slope;

wherein the gentle slope is formed on the substrate by the steps of;

forming a first resist layer on the substrate in a stripe form;

subjecting the stripe-shaped resist layer to heat-treatment so that the edges of the stripe-shaped resist layer are rounded;

covering the substrate and stripe-shaped resist layer on regions other than where the gentle slope is to be formed at one side; and

etching the exposed substrate by ion beam etching.

6. A method according to claim 5, wherein said substrate is semi-insulating GaAs.

7. A method according to claim 5, wherein said optical semiconductor element is a laser diode or a photo-diode.

8. A method according to claim 5, wherein said electronic semiconductor is a field effect transistor.