Method and circuit for manipulation-proof devaluation of EEPROMS

• US 5,001,332 A
• Filed: 12/19/1988
• Issued: 03/19/1991
• Est. Priority Date: 12/17/1987
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Schrenk, Hartmut
• Primary Examiner(s): Trafton, David
• Application Number:
  US07/286,520
• Time in Patent Office: 820 Days
• Field of Search: 235/436, 235/441, 235/492
• US Class Current: 235/492
• CPC Class Codes: G07F 7/0866 by active credit-cards adapted therefor G07F7/1008 takes precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

A debit card includes at least one address and control logic circuit and a nonvolatile memory having a zone with memory locations provided for storing updated devaluation status of the debit card. At least part of the memory is electrically erasable and all of the memory locations of the zone of the nonvolatile memory can be read out and written upon bit by bit. A method and circuit for devaluation of a monolithically integrable electronic circuit of the debit card includes dividing the zone of the nonvolatile memory into partial zones each having a different value in the form of a multi-stage counter. A simultaneous erasure of the memory cells is permitted only for all of the memory cells of one partial zone of a given value. Erasure of each partial zone is permitted only after a transfer bit has been written into a previously unwritten memory cell of the partial zone of next-higher value. Writing-in is monitored with a logic circuit. An erasure of the partial zone of the highest value is permitted only under special conditions.

Claims

1. Method for devaluation of a monolithically integrable electronic circuit of a debit card, including at least one address and control logic circuit and a nonvolatile memory having a zone with memory locations provided for storing updated devaluation status of the debit card, at least part of the memory being electrically erasable and all of the memory locations of the zone of the nonvolatile memory can be read out and written upon bit by bit, which comprises dividing the zone of the nonvolatile memory into partial zones each having a different value in the form of a multi-stage counter, permitting a simultaneous erasure of the memory cells only for all of the memory cells of one partial zone of a given value, and permitting erasure of each partial zone only after a transfer bit has been written into a previously unwritten memory cell of the partial zone of next-higher value, monitoring writing-in with a logic circuit, and permitting an erasure of the partial zone of the highest value only under special conditions.

2. Method according to claim 1, which comprises irreversibly suppressing an erasure of the partial zone of highest value.

3. Method according to claim 1, which comprises irreversibly suppressing an erasure of the partial zone of highest value by destruction of a fusible cutout.

4. Monolithically integrable circuit for devaluation of a monolithically integrable electronic circuit of a debit card having at least one address and control logic circuit and a nonvolatile memory having a zone with memory locations provided for storing updated devaluation status of the debit card, at least part of the memory being electrically erasable and all of the memory locations of the zone of the nonvolatile memory can be read out and written upon bit by bit, the circuit comprising an electrically erasable memory with a matrix of two-transistor memory cells each including a selection transistor, a memory transistor and a control line, line selection lines and column selection lines for individually selecting said memory cells, common control lines connected linewise to the gate terminals of said memory cells, the drain terminals of said selection transistors being connected columnwise to said column selection lines, load elements each connecting a respective one of said column selection lines to a programming potential, a common first circuit node, switching transistors each being connected through a respective one of said column selection lines to said first circuit node, the gate terminals of said switching transistors being connected to and triggered by said column selection lines, a common second circuit node, other switching transistors each connecting a respective control line of said memory cells to said second circuit node, the gate terminal of each of said other switching transistors being connected to said line selection line of the zone of next-higher value, a specially secured line triggering the gate terminal of said other switching transistor of the zone of the highest value, an erasure switching transistor connecting said second circuit node to an erasing potential, and a logic circuit controlling the switching state of said erasure switching transistor.

5. Monolithically integrable circuit according to claim 4, wherein said specially secured line includes a fusible cutout.

6. Monolithically integrable circuit according to claim 4, wherein said specially secured line is activatable only with the use of a security code.

7. Monolithically integrable circuit according to claim 4, including first and second AND gates each having two inputs and an output, an inverting circuit having an input connected to said first circuit node and an output connected to one of said inputs of said second AND gate, said first circuit node also being connected to one of said inputs of said first AND gate, the other of said inputs of said first AND gate being subjected to an evaluation signal, and a flip-flop having a setting input connected to said output of said first AND gate, a reset input acted upon by a reset signal from the address logic circuit upon each address change, and an output connected to the other of said inputs of said second AND gate, and said output of said second AND gate being connected to the control input of said erasure switching transistor.