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Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof

  • US 5,001,526 A
  • Filed: 11/07/1988
  • Issued: 03/19/1991
  • Est. Priority Date: 11/10/1987
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device having a memory cell including a transistor stacked on a capacitor thereof, a word line and a bit line, said semiconductor memory device comprising:

  • (a) a first insulating layer formable on a semiconductor substrate;

    (b) a plurality of semiconductor pillar structures formed on said first insulating layer and being arranged in a matrix array and isolated from each other by a trench extending to said first insulating layer, each said pillar structure having a first semiconductor layer of a first conductivity type formed on said first insulating layer and forming a storage electrode of said capacitor, a second semiconductor layer of a second conductivity type opposite to the first conductivity type formed on said first semiconductor layer, and a third semiconductor layer of the first conductivity type formed on said second semiconductor layer, and said transistor being formed in an upper portion of each pillar structure, each said pillar structure having side surfaces;

    (c) second insulating layer formed on the side surfaces of each said pillar structure and having first and second regions, the first region being an insulating layer of said capacitor and the second region a gate insulating layer of said transistor;

    (d) a first conductive layer forming a cell plate of said capacitor and being formed in said trench and on said first insulating layer, said first conductive layer having substantially the same thickness as the first semiconductor layer of said pillar structure and sandwiching the first region of said second insulating layer with said first semiconductor layer;

    (e) a third insulating layer formed on said first conductive layer;

    (f) a second conductive layer formed over said third insulating layer and the second region of said insulating layer, said second conductive layer surrounding at least a portion of said second semiconductor layer of said pillar structure and forming a gate electrode of said transistor, separated from adjacent second conductive layers in a first direction and connected with adjacent second conductive layers in a second direction different from the first direction so as to form said word line;

    (g) a third conductive layer formed on said third semiconductor layer and connected with adjacent third semiconductor layers of said pillar structure along the first direction so as to form said bit line; and

    wherein said second semiconductor layer of the second conductivity type includes a lower second semiconductor layer having an impurity concentration and an upper second semiconductor layer having a relatively high impurity concentration compared to the lower second semiconductor layer.

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