Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof

• US 5,001,526 A
• Filed: 11/07/1988
• Issued: 03/19/1991
• Est. Priority Date: 11/10/1987
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Gotou, Hiroshi
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Bowers, Courtney A.
• Application Number:
  US07/268,185
• Time in Patent Office: 862 Days
• Field of Search: 357/23.6, 357/49, 357/23.4, 357/45
• US Class Current: 257/302
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A DRAM cell structure and a manufacturing method thereof as disclosed, in which a transistor and a capacitor are formed three-dimensionally in an SOI structure. The substrate having the SOI structure is fabricated by bonding two silicon substrates sandwiching a silicon oxide layer therebetween. A plurality of pillars of silicon layers arranged in a matrix array is formed in the SOI structure by forming a trench in the silicon layers of the SOI. The lower portion of the pillar is used as a storage electrode of the capacitor and the upper portion, as active regions of the vertical transistor. In the trench, doped polysilicon is filled in a lower portion and functions as a cell plate of the capacitor, with a dielectric film being formed on the pillar surface. A gate insulating film and a gate electrode thereon are formed on the upper side surface of the pillar. The gate electrode is self-aligned, connected in the Y-direction but separated in the X-direction, and functions as a word line. A connecting line of the upper active region of the transistor functions as a bit line. Only two mask processes are needed in fabricating the DRAM cell, and isolation between adjacent cells is excellent in spite of a small cell area.

Claims

1. A semiconductor memory device having a memory cell including a transistor stacked on a capacitor thereof, a word line and a bit line, said semiconductor memory device comprising:

(a) a first insulating layer formable on a semiconductor substrate;

(b) a plurality of semiconductor pillar structures formed on said first insulating layer and being arranged in a matrix array and isolated from each other by a trench extending to said first insulating layer, each said pillar structure having a first semiconductor layer of a first conductivity type formed on said first insulating layer and forming a storage electrode of said capacitor, a second semiconductor layer of a second conductivity type opposite to the first conductivity type formed on said first semiconductor layer, and a third semiconductor layer of the first conductivity type formed on said second semiconductor layer, and said transistor being formed in an upper portion of each pillar structure, each said pillar structure having side surfaces;

(c) second insulating layer formed on the side surfaces of each said pillar structure and having first and second regions, the first region being an insulating layer of said capacitor and the second region a gate insulating layer of said transistor;

(d) a first conductive layer forming a cell plate of said capacitor and being formed in said trench and on said first insulating layer, said first conductive layer having substantially the same thickness as the first semiconductor layer of said pillar structure and sandwiching the first region of said second insulating layer with said first semiconductor layer;

(e) a third insulating layer formed on said first conductive layer;

(f) a second conductive layer formed over said third insulating layer and the second region of said insulating layer, said second conductive layer surrounding at least a portion of said second semiconductor layer of said pillar structure and forming a gate electrode of said transistor, separated from adjacent second conductive layers in a first direction and connected with adjacent second conductive layers in a second direction different from the first direction so as to form said word line;

(g) a third conductive layer formed on said third semiconductor layer and connected with adjacent third semiconductor layers of said pillar structure along the first direction so as to form said bit line; and

wherein said second semiconductor layer of the second conductivity type includes a lower second semiconductor layer having an impurity concentration and an upper second semiconductor layer having a relatively high impurity concentration compared to the lower second semiconductor layer.

2. A semiconductor memory device having a memory cell according to claim 1, wherein the impurity concentration of the lower second semiconductor layer is about one tenth that of the upper second semiconductor layer.

3. A semiconductor memory device having a memory cell according to claim 1, wherein a surface level of said first conductive layer is within a height range of the lower second semiconductor layer of said second semiconductor layer.

4. A semiconductor memory device having a memory cell according to claim 1, wherein said plurality of semiconductor pillar structures are arranged in the matrix array with a gap formed between adjacent pillar structures in a first direction being of greater distance than a gap formed between adjacent pillar structures in a second direction.

5. A semiconductor memory device having a memory cell according to claim 1, wherein said second conductive layer is made of doped polysilicon and has a curved surface and a thickness that decreases with increasing height.

6. A semiconductor memory device having a memory cell including a transistor stacked on a capacitor thereof, a word line and a bit line, said semiconductor memory device comprising:

(a) a first insulating layer formable on a semiconductor substrate;

(b) a plurality of semiconductor pillar structures formed on said first insulating layer and being arranged in a matrix array and isolated by a trench extending to said first insulating layer, each said pillar structure having a first semiconductor layer of a first conductivity type of a relatively low impurity concentration formed on said first insulating layer, a second semiconductor layer of the first conductivity type of a high impurity concentration relative to the first semiconductor layer and being formed on said first semiconductor layer, and a third semiconductor layer of a second conductivity type formed on said second semiconductor layer, and said transistor being formed in an upper portion of each pillar structure and said capacitor being formed in a lower portion of each pillar structure, each said pillar structure having side surfaces;

(c) a second insulating layer formed over the side surfaces of said pillar structure and having first and second regions, the first region being an insulating layer of said capacitor and the second region being a gate insulating layer of said transistor;

(d) a first conductive layer forming a cell plate of said capacitor and being formed in said trench and on said first insulating layer, said first conductive layer having substantially the same thickness as the first semiconductor layer of said pillar structure and sandwiching the first region of said second insulating layer with said first semiconductor layer;

(e) a third insulating layer formed on said first conductive layer;

(f) a second conductive layer formed over said third insulating layer and the second region of said second insulating layer, said second conductive layer surrounding said second semiconductor layer of each said pillar structure and forming a gate electrode of said transistor, separated from adjacent second conductive layers in a first direction and connected with adjacent second conductive layers in a second direction different from the first direction, so as to form said word line; and

(g) a third conductive layer formed on said third semiconductor layer and connected with adjacent third semiconductor layers of said pillar structure along the first direction so as to form said bit line.

7. A semiconductor memory device having a memory cell according to claim 6, wherein said semiconductor substrate is of the first conductivity type and a hole is formed in said first insulating layer under each said pillar structure and said first semiconductor layer contacts the substrate through said hole.

8. A semiconductor memory device having a memory cell according to claim 6, wherein said plurality of semiconductor pillar structures are arranged in the matrix array with a gap formed between adjacent pillar structures in a first direction being of greater distance than a gap formed between adjacent pillar structures in a second direction.

9. A semiconductor memory device having a memory cell according to claim 6, wherein said second conductive layer is made of doped polysilicon and has a curved surface and a thickness that decreases with increasing height.