Radiation hardened CMOS on SOI or SOS devices

• US 5,001,528 A
• Filed: 01/31/1989
• Issued: 03/19/1991
• Est. Priority Date: 01/31/1989
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Bahraman, Ali
• Primary Examiner(s): PRENTY, MARK V
• Application Number:
  US07/304,759
• Time in Patent Office: 777 Days
• Field of Search: 357/23.7, 357/4, 357/42, 357/49, 357/23.11, 437/938
• US Class Current: 257/351
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: Y10S 257/906 Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

Abstract

A radiation hardened CMOS transistor has a source region, drain region and channel region formed on an SOI or SOS wafer. End plugs of opposite conductivity to that of the source and drain regions are connected to the channel region. In one embodiment, the end plugs extend along opposite ends of the source region but not along the drain region. In another embodiment, the end plugs extend along opposite ends of the source region and the drain region, and the drain region includes portions adjacent the end plugs having an impurity concentration which is significantly lower than the impurity concentration of the remainder of the drain region. The transistor is surrounded by a silicon dioxide isolation region. Contact holes for establishing electrical contact are positioned over areas in which the source region interfaces with each of the end plugs, and over an area of the drain region. The end plugs are electrically tied to the source region through common metallized contacts so that radiation sensitive parasitic actions may be prevented.

Claims

1. A radiation hardened MOS SOI or SOS transistor comprising:

a silicon-on-insulator or a silicon-on-sapphire wafer;

a source region formed on said wafer;

a drain region formed on said wafer;

a channel region formed on said wafer between and contiguous with said source region and said drain region;

said source region and said drain region being of one conductivity type and said channel being of an opposite conductivity type;

end plugs connected to said channel region and extending along opposite ends of said source region but not along said drain region, said end plugs being of the same conductivity type as said channel region but of a higher impurity concentration, and said end plugs having a conductivity which is opposite to that of said source region; and

means for establishing electrical contact with said drain region, said channel region, and with said source region and each of said end plugs.

2. The transistor of claim 1, further including a silicon dioxide isolation region surrounding said transistor.

3. The transistor of claim 1, wherein said source region, drain region, and channel region are of a conductivity type forming an NMOS transistor.

4. The transistor of claim 1, wherein said source region, drain region, and channel region are of a conductivity type forming a PMOS transistor.

5. The transistor of claim 1, further including a layer of buried oxide between said wafer and said source region, drain region and channel region.

6. The transistor of claim 1, wherein said end plugs are made of silicon.