Electrostatic handling device

• US 5,001,594 A
• Filed: 09/06/1989
• Issued: 03/19/1991
• Est. Priority Date: 09/06/1989
• Status: Expired due to Fees

• Current Assignee: MCNC, Inc.
• Original Assignee: MCNC, Inc.
• Inventors: Bobbio, Stephen M.
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Gaffin, Jeffrey A.
• Application Number:
  US07/403,755
• Time in Patent Office: 559 Days
• Field of Search: 361/230, 361/233, 361/234, 269/8, 269/289 R, 269/903
• US Class Current: 361/234
• CPC Class Codes: H01L 21/6831 using electrostatic chucks
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks

Abstract

An electrostatic handling device for a wafer having a pair of faces, includes a dielectric region having a top face which is adapted to accept one of the pair of wafer faces thereagainst. Conductors are positioned in the dielectric region. The conductors are arranged in the dielectric region to generate electrostatic force between the conductors and the wafer to hold the wafer against the top face of the dielectric region. The conductors are further arranged in the dielectric region to generate substantially no net electrostatic force at the opposite one of the pair of wafer faces to thereby reduce electrostatic force interference thereat.

Claims

1. An electrostatic handling device for a wafer having a pair of wafer faces, comprising:

a dielectric region having a top face, said top face being adapted for accepting one of the pair of wafer faces thereagainst; and

a plurality of conductors in said dielectric region, at least one of the spacings between said plurality of conductors and the spacing from said plurality of conductors to said top face of said dielectric region being arranged to generate electrostatic force between said conductors and the wafer to thereby hold the wafer against said top face when said conductors are electrically charged, at least one of the spacings between said plurality of conductors and the spacing from said plurality of conductors to said top face of said dielectric region being arranged to generate substantially no net electrostatic force at the opposite one of the pair of wafer faces to thereby reduce electrostatic force interference thereat when said conductors are electrically charged.

2. The electrostatic handling device according to claim 1 wherein said plurality of conductors are arranged to have a spacing between each other which is less than the spacing between the pair of wafer faces.

3. The electrostatic handling device according to claim 1 wherein said plurality of conductors are arranged to have a spacing between each other which is greater than the spacing from said plurality of conductors to said top face of said dielectric region.

4. The electrostatic handling device according to claim 1 wherein the spacing from said plurality of conductors to said top face of said dielectric region is substantially less than one third of said spacing between said conductors.

5. The electrostatic handling device of claim 1 wherein the spacing from said plurality of conductors to said top face of said dielectric region plus the spacing between the pair of wafer faces is greater than two thirds of said spacing between said conductors.

6. The electrostatic handling device according to claim 2 wherein said plurality of conductors are arranged to have a spacing between each other which is greater than the spacing from said plurality of conductors to said top face of said dielectric region.

7. The electrostatic handling device according to claim 2 wherein the spacing from said plurality of conductors to said top face of said dielectric region is substantially less than one third of said spacing between said conductors.

8. The electrostatic handling device according to claim 2 wherein the spacing from said plurality of conductors to said top face of said dielectric region plus the spacing between the pair of wafer faces is greater than two thirds of said spacing between said conductors.

9. The electrostatic handling device according to claim 6 wherein the spacing from said plurality of conductors to said top face of said dielectric region plus the spacing between the pair of wafer faces is greater than two thirds of said spacing between said conductors.

10. The electrostatic handling device according to claim 7 wherein the spacing from said plurality of conductors to said top face of said dielectric region plus the spacing between the pair of wafer faces is greater than two thirds of said spacing between said conductors.

11. The electrostatic handling device according to claim 3 wherein the spacing from said plurality of conductors to said top face of said dielectric region plus the spacing between the pair of wafer faces is greater than two thirds of said spacing between said conductors.

12. The electrostatic handling device according to claim 4 wherein the spacing from said plurality of conductors to said top face of said dielectric region plus the spacing between the pair of wafer faces is greater than two thirds of said spacing between said conductors.

13. The electrostatic handling device according to claim 1 wherein said dielectric region has a bottom face, said electrostatic handling device further comprising a support structure having a top face positioned against said bottom face of said dielectric region.

14. The electrostatic handling device according to claim 1 wherein said plurality of conductors comprise a first group of conductors adapted to be charged positively and a second group of conductors adapted to be charged negatively.

15. The electrostatic handling device according to claim 14 wherein said first group of conductors is connected to a first voltage source and said second group of conductors is connected to a second voltage source.

16. The electrostatic handling device according to claim 14 wherein said conductors in said first and second groups are interdigitated, with a predetermined spacing between adjacent conductors.

17. The electrostatic handling device according to claim 16 wherein said conductors in said first and second groups are interdigitated in C-shaped concentric rings which lie in a plane parallel to said top face of said dielectric region.

18. The electrostatic handling device according to claim 16 wherein said conductors in said first and second groups are interdigitated in parallel lines which lie in a plane parallel to said top face of said dielectric region.

19. The electrostatic handling device according to claim 1 wherein said dielectric region is formed of a material selected from the group consisting of silicon dioxide, silicon nitride, and polyimide.

20. A method for holding the bottom face of a wafer against a dielectric surface comprising the step of:

generating electrostatic force between the wafer and the dielectric surface which produce substantially no net electrostatic force at the top face of the wafer, whereby the top face of the wafer may be processed without electrostatic force interference.

21. The method according to claim 20 wherein said dielectric surface is formed of a material selected from the group consisting of silicon dioxide, silicon nitride, and polyimide.