Complex multiplexer/demultiplexer apparatus

• US 5,001,711 A
• Filed: 08/03/1989
• Issued: 03/19/1991
• Est. Priority Date: 08/03/1988
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Obana, Yuji, Hiramoto, Masanori
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Hsu, Alpus H.
• Application Number:
  US07/389,264
• Time in Patent Office: 593 Days
• Field of Search: 370/84, 370/112, 370/102, 370/110.1
• US Class Current: 370/535
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH
• CPC Class Codes: H04J 3/1641 Hierarchical systems

Abstract

A complex multiplexer/demultiplexer apparatus which converts input low order group data signals to middle order group data signals and multiplexes them to high order group data signals and converts high order group data signals to middle order group data signals and demultiplexes them to low order group data signals, wherein a plurality of low order group channels are processed by multiplexing and demultiplexing at a second clock bit synchronized with a first clock on the high order group side, the second clock including empty bits, and the bit rate being set lower than the first clock, and signal speeds between each of first multiplexers and a second multiplexer and between a first demultiplexer and each of second demultiplexers are converted by insertion and deletion of the empty bits which may have inserted therein additional information.

Claims

1. A complex multiplexer/demultiplexer apparatus which comprises:

a plurality of first multiplex means for multiplexing input low order group data signals to convert them into middle order group data signals,

second multiplex means for multiplexing the middle order group data signals to convert them into high order group data signals,

first demultiplex means for demultiplexing the input high order group data signals to convert them into middle order group data signals,

a plurality of second demultiplex means for demultiplexing the middle order group data signals to convert them into low order group data signals,

a plurality of first speed conversion means connected to said plurality of first multiplex means, for inserting empty bits in the middle order group data signals,

a plurality of second speed conversion means, connected to the second multiplex means, for deleting the empty bits from the middle order group data signals, and

clock generating means for supplying timing clocks required by the above means, the multiplexing in the plurality of first multiplex means being performed based on a common timing clock related to the timing clock used in the multiplexing in the second multiplex means.

2. An apparatus according to claim 1, wherein the second multiplex means operates in synchronization with a basic clock signal generated by the clock generating means, the first multiplex means operates in synchronization with a middle order group data clock which is formed by applying speed conversion to a middle order group common clock formed by frequency dividing the basic clock signal, the middle order group data clock being bit synchronized with the middle order group common clock, but the middle order group data clock including empty bits which are produced at a fixed cycle and the clock rate of the middle order group data signal being lower than the clock rate of the middle order group common clock.

3. An apparatus according to claim 1, wherein the middle order group data signals transfer control data in the empty bits between the first and second speed conversion means.

4. An apparatus according to claim 2, wherein additional information bits are inserted in the empty bits and the additional information bits include stuffing indication bits.

5. An apparatus according to claim 4, wherein the insertion of the additional information bits is performed by the first speed conversion means, and the second speed conversion means deletes the inserted additional information bits, converts the speed, extracts the additional information bits, and supplies the extracted additional information bits for control at the corresponding second multiplex means.

6. An apparatus according to claim 5, wherein the clock generating means includes a frame timing pulse generating unit, which frame timing pulse generating unit generates a frame timing pulse synchronized with the basic clock signal based on the multiplexing operation in the second multiplex means, generates empty bits in the first speed conversion means synchronized with the frame timing pulse, and inserts additional information bits in the empty bits.

7. An apparatus according to claim 6, wherein the first speed conversion means include a clock generating unit which receives as input the middle order group common clock and the frame timing pulse and outputs the middle order group data clock.

8. An apparatus according to claim 7, wherein the first speed conversion means includes an additional information bit insertion unit which inserts additional information bits into the empty bits in the middle order group data clock generated in the clock generating unit and which transmits the middle order group data signal synchronized with the middle order group common clock to the corresponding second speed conversion means.

9. An apparatus according to claim 8, which has, in the second speed conversion means, an additional information deletion unit which deletes additional information bits from the middle order group data signal received from the corresponding first speed conversion means, an additional information bit extraction unit which extracts additional information bits from the middle order group data signal, a stuffing detection unit which detects stuffing based on the extracted additional information bits, and a destuffing control unit which performs destuffing on the middle order group data signal passing through the additional information deletion unit based on the detected stuffing.

10. An apparatus according to claim 9, which is provided with a jitter removing variable slot at a part of a data bit train having at its head a stuffing indication bit, the variable slot being used as the control bit for the jitter removal when a stuffing request pulse is output from the corresponding first multiplex means and being used as the data bit forming part of the data bit train when the stuffing request pulse is output.

11. an apparatus according to claim 10, wherein the clock generating unit in the first speed conversion means comprises:

a first frequency divider and a second frequency divider connected in cascade, the first frequency divider receives the middle order group common clock and frame timing pulse and the second frequency divider receives at least the frame timing pulse,

a flip flop which receives the output of the second frequency divider as a clock input and is set by the stuffing request pulse,

a first variable slot pulse generator which receives as input the output of the second frequency divider, the middle order group common clock, and the output of the flip flop, and

a first OR gate which receives as input the output of the first variable slot pulse generator, the middle order group common clock, and the frame timing pulse, the middle order data clock being output from the first OR gate, and

wherein the additional information bit insertion unit in the first speed conversion means comprises;

a first AND gate which receives as input the output of the first frequency divider and the output of the flip flop, and

a multiplexer unit which multiplexes the output of the first AND gate, the output of the variable slot pulse generator, and the middle order group data signal from the corresponding first multiplexer unit, the output of the multiplexer unit being supplied to the corresponding speed conversion means.

12. an apparatus according to claim 11, wherein the second speed conversion means each is comprised of:

a third frequency divider and a fourth frequency divider which respectively receive the second order group common clock and frame timing pulse and are connected in cascade,

a second variable slot pulse generator which receives as input the output of the fourth frequency divider and the middle order group common clock,

a second AND gate which receives as input the output of the third frequency divider and the middle order group data signal from the first speed conversion means,

an additional information bit detector which receives the output of the second AND gate and detects the additional information bits,

a third AND gate which receives as input the detection output from the additional information bit detector and the output of the second variable slot pulse generator,

a second OR gate which receives as input the output of the third AND gate, the output of the third frequency divider, and the middle order group common clock, and

an elastic memory which is subjected to read control by the output of the second OR gate and the write clock synchronized with the middle order group data clock from the corresponding second multiplexer unit and which receives the middle order group data signal,

the detection output from the additional information bit detector being supplied as the stuffing request to the corresponding second multiplexer unit and being supplied as the middle order group data signal to multiplex the output of the elastic memory.

13. A complex multiplexer/demultiplexer apparatus which comprises:

a plurality of first multiplex means for multiplexing input low order group data signals to convert them into middle order group data signals,

second multiplex means for multiplexing the middle order group data signals to convert them into high order group data signals,

first demultiplex means for demultiplexing the input high order group data signals to convert them into middle order group data signals,

a plurality of second demultiplex means for demultiplexing the middle order group data signals to convert them into low order group data signals,

a plurality of first speed conversion means connected to the plurality of first multiplex means to insert empty bits in the middle order group data signals,

a plurality of second speed conversion means connected to the second multiplex means to delete the empty bits from the middle order group data signals, and

clock generating means for supplying timing clocks required by the above means, the demultiplexing in the plurality of second demultiplex means being performed based on a common timing clock related to the timing clock used in the multiplexing in the second multiplex means.

14. An apparatus according to claim 13, wherein the second demultiplex means operates in synchronization with a basic clock signal generated by the clock generating means, the first demultiplex means operates in synchronization with a middle order group data clock which is formed by applying speed conversion to a middle order group common clock formed by frequency dividing the basic clock signal extracted from an input high order group data signal, the middle order group data clock being bit synchronized with the middle order group common clock formed by frequency dividing the basic clock signal, but the middle order group data clock including empty bits which are produced at a fixed cycle and the clock rate of the middle order group data clock being lower than the clock rate of the middle order group common clock.

15. An apparatus according to claim 14, further including:

a plurality of third speed conversion means connected to the first demultiplex means, and

a plurality of fourth speed conversion means connected to the plurality of second demultiplex means, the third speed conversion means generating the empty bits and the fourth speed conversion means deleting the empty bits, the middle order group data signals having the empty bits and being transferred between the third and fourth speed conversion means synchronized with the middle order group common clock.

16. An apparatus according to claim 15, wherein additional information bits are inserted in the empty bits and the additional information bits include stuffing indication bits.

17. An apparatus according to claim 16, wherein the insertion of the additional information bits is performed by the third speed conversion means, and the fourth speed conversion means deletes the inserted additional information bits, converts the speed, extracts the additional information bits, and supplies the extracted additional information bits for control at the corresponding second demultiplex means.

18. An apparatus according to claim 17, wherein the clock generating means includes a frame timing pulse generating unit, which frame timing pulse generating unit generates a frame timing pulse synchronized with the basic clock signal based on the multiplexing operation in the second multiplex means, generates empty bits in the third speed conversion means synchronized with the frame timing pulse, and inserts additional information bits in the empty bits.

19. An apparatus according to claim 18, wherein the third speed conversion means have a stuffing control unit which receives as input the middle order group common clock and the frame timing pulse and outputs the middle order group data clock.

20. An apparatus according to claim 19, which has, in the third speed conversion means, an additional information bit insertion unit which inserts additional information bits into the empty bits in the middle order group data clock generated in the stuffing control unit and which transmits the middle order group data signal synchronized with the middle order group common clock to the corresponding fourth speed conversion means.

21. An apparatus according to claim 20, which has, in the fourth speed conversion means, an additional information deletion unit which deletes additional information bits from the middle order group data signal received from the corresponding third speed conversion means, an additional information bit extraction unit which extracts additional information bits from the middle order group data signal, a stuffing detection unit which detects stuffing based on the extracted additional information bits, and a destuffing control unit which performs destuffing on the middle order group data signal passing through the additional information deletion unit based on the detected stuffing.

22. An apparatus according to claim 21, which is provided with a jitter removing variable slot at a part of a data bit train having at its head a stuffing indication bit, the variable slot being used as the control bit for the jitter removal when a stuffing request is generated in the corresponding third speed conversion means and being used as the data bit forming part of the data bit train when the stuffing request is generated.

23. An apparatus according to claim 22, wherein the third speed conversion means comprises:

a first frequency divider and a second frequency divider connected in cascade, the first frequency divider receiving the middle order group common clock and frame timing pulse and the second frequency divider receiving at least the frame timing pulse,

a flip flop which receives the output of the second frequency divider as a clock input and is set by the generation of the stuffing request,

a first variable slot pulse generator which receives as input the output of the second frequency divider, the middle order group common clock, and the output of the flip flop, and

a first OR gate which receives as input the output of the first variable slot pulse generator, the middle order group common clock, and the output of the first frequency divider,

a phase comparator which receives the output of the first OR gate and the write clock synchronized with the middle order group data clock supplied from the first demultiplex means, compares the phase of the output of the first OR gate and the write clock, based on the results of the comparison generates the stuffing request when the phase deviation is large, and sets the stuffing request pulse in the flip flop,

a memory which stores middle order group data signals supplied from the first demultiplex means by the write clock and is read out by the output of the first OR gate,

a first AND gate which receives as input the output of the flip flop and the output of the first frequency divider, and

a multiplexer unit which multiplexes the output of the first AND gate, the output of the first variable slot pulse generator, and the middle order group data signal read out from the memory,

the output of the multiplexer unit being supplied to the corresponding fourth speed conversion means.

24. An apparatus according to claim 23, wherein the fourth speed conversion means each is comprised of:

a third frequency divider and a fourth frequency divider which respectively receive the middle order group common clock and frame timing pulse and are connected in cascade,

a second variable slot pulse generator which receives as input the output of the fourth frequency divider and the middle order group common clock,

a second AND gate which receives as input the output of the third frequency divider and the middle order group data signal from the third speed conversion means,

an additional information bit detector which receives the output of the second AND gate and detects the additional information bits,

a third AND gate which receives as input the detection output from the additional information bit detector and the output of the second variable slot pulse generator, and

a second OR gate which receives as input the output of the third AND gate, the output of the third frequency divider, and the middle order group common clock,

the output from the second OR gate being used as the middle order group data clock and supplied together with the middle order group data signal to the second demultiplex means.

25. An apparatus according to claim 15, wherein the second multiplex means operates in synchronization with the basic clock signal generated by the clock generating means, the first multiplex means operates in synchronization with the middle order group data clock formed by applying speed conversion to the middle order group common clock formed by frequency dividing the basic clock signal, the middle order group data clock being bit synchronized with the middle order group common clock, but the middle order group data clock including empty bits which are produced at a fixed cycle and the clock rate of the middle order group data clock being lower than the clock rate of the middle order group common clock.

26. A complex multiplexer apparatus, said apparatus comprising:

a first multiplexer to convert a plurality of input low order group data signals into a plurality of middle order group data signals,

a second multiplexer to convert the pluality of middle order group data signals into high order group data signals,

a first speed converter connected to said first multiplexer to insert empty bits in the middle order group data signal,

a second speed converter connected to said second multiplexer to delete the empty bits from the middle order group data signal, and

a clock source to supply a basic clock signal as a time base for the multiplexer apparatus.

27. An apparatus according to claim 26, wherein said second multiplexer operates in synchronization with the basic clock signal generated by the clock source, said first multiplexer operates in synchronization with a middle order group data clock formed by speed conversion by said first speed converter of a middle order group common clock formed by frequency dividing the basic clock signal, the middle order group data clock having a clock rate lower than the clock rate of the middle order group common clock.

28. An apparatus according to claim 26, wherein said first speed converter inserts additional information bits in the empty bits and the additional information bits include stuffing indication bits.

29. An apparatus according to claim 28, wherein said second speed converter deletes the inserted additional information bits, converts the speed, extracts the additional information bits, and supplies the extracted additional information bits for control at said second multiplexer.

30. An apparatus according to claim 29, wherein the clock source includes a frame timing pulse generating unit to generate a frame timing pulse synchronized with the basic clock signal based on said second multiplexer.

31. A complex demultiplexer apparatus, said apparatus comprising:

a first demultiplexer to convert an input high order group data signal into a plurality of middle order group data signals,

a second demultiplexer to convert the plurality of middle order group data signals into a plurality of low order group data signals,

a first speed converter connected to said first demultiplexer to insert empty bits in the middle order group data signal,

a second speed converter connected to said second demultiplexer to delete the empty bits from the middle order group data signal, and

a clock source to supply a basic clock signal as a time base for the demultiplexer apparatus.

32. An apparatus according to claim 31, wherein said second demultiplexer operates in synchronization with the basic clock signal generated by the clock source, said first demultiplexer operates in synchronization with a middle order group data clock which is formed by applying speed conversion in said first speed converter to a middle order group common clock formed by frequency dividing the basic clock signal, the middle order group data clock having a clock rate lower than the clock rate of the middle order group common clock.

33. An apparatus according to claim 31, wherein said first speed converter inserts additional information bits in the empty bits and the additional information bits include stuffing indication bits.

34. An apparatus according to claim 33, wherein said second speed converter deletes the inserted additional information bits, converts the inserted additional information bits, converts the speed, extracts the additional information bits, and supplies the extracted additional information bits for control at said second demultiplexer.

35. An apparatus according to claim 34, wherein the clock source includes a frame timing pulse generating unit to generate a frame timing pulse synchronized with the basic clock signal based on the said second multiplexer.

36. An apparatus according to claim 35, wherein said first speed converter includes a stuffing control unit receiving as input the middle order group common clock and the frame timing pulse and outputting the middle order group data clock.

37. An apparatus according to claim 36, wherein said first speed converter includes an additional information bit insertion unit to insert additional information bits into the empty bits in the middle order group data clock generated in the stuffing control unit and to transmit the middle order group data signal synchronized with the middle order group common clock to said second speed converter.

38. An apparatus according to claim 37, wherein the second speed converter includes:

an additional information deletion unit to delete additional information bits from the middle order group data signal received from said first speed converter,

an additional information bit extraction unit to extract additional information bits from the middle order group data signal,

a stuffing detection unit to detect stuffing based on the extracted additional information bits, and

a destuffing control unit to perform destuffing on the middle order group data signal passing through the additional information deletion unit based on the detected stuffing.