Thin film transistor array

• US 5,003,356 A
• Filed: 04/02/1990
• Issued: 03/26/1991
• Est. Priority Date: 09/09/1987
• Status: Expired due to Term

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Kanbara, Minoru, Yamamura, Nobuyuki, Wakai, Haruo, Sato, Syunichi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): SAADAT, MAHSHID D
• Application Number:
  US07/503,268
• Time in Patent Office: 358 Days
• Field of Search: 357/4, 357/23.7, 357/71, 357/2, 350/334, 350/336
• US Class Current: 257/390
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A TFT array having a plurality of gate lines and a plurality of drain lines formed on a transparent substrate. The gate lines intersect with the drain lines. TFT are formed at the intersections of the gate lines and the drain lines. An insulating film is formed on the drain lines and the drain electrodes of the TFTs. Pixel electrodes are formed, each overlapping the corresponding gate line and the corresponding drain line. The pixel electrode has a large area and thus, have a high opening ratio. The TFT array can, therefore, help to provide a liquid crystal display having high contrast.

Claims

1. A TFT array comprising:

a transparent insulating substrate;

a plurality of gate lines formed on said transparent insulating substrate;

a plurality of drain lines formed on said transparent insulating substrate and intersecting with said gate lines;

thin film transistors located at the intersections of said gate lines and said drain lines, each having at least a gate electrode, a semiconductor layer, a source electrode, and a drain electrode;

an insulating film covering at least said drain electrodes and said drain lines; and

a transparent electrode electrically connected to said source electrodes and overlapping said gate lines and said drain lines.

2. The TFT array according to claim 1, wherein said transparent electrode is a pixel electrode.

3. The TFT array according to claim 1, wherein said source electrodes are directly connected to said transparent electrode electrically.