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Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis

  • US 5,003,487 A
  • Filed: 06/28/1988
  • Issued: 03/26/1991
  • Est. Priority Date: 06/28/1988
  • Status: Expired due to Fees
First Claim
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1. A method of logic synthesis that avoids producing the uncorrectable timing problems that are encountered when rules for a given technology are assigned to a technology independent logic model, said given technology having a prescribed set of available functional logic blocks, said method comprising the steps of:

  • (a) identifying logic blocks in the model that are not available in said given technology;

    (b) estimating the timing characteristics of said logic blocks that are not available in said given technology based upon the characteristics of similar logic blocks that are available, thereby providing a preliminary model;

    (c) calculating the timing values for the preliminary model using fan-out values that are limited to a predetermined maximum load;

    (d) applying timing correction routines to the critical path in the preliminary model, thereby providing an estimated model; and

    (e) correcting violations of the rules of said given technology in the estimated model, thereby providing a technology-legal model.

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