Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis

• US 5,003,487 A
• Filed: 06/28/1988
• Issued: 03/26/1991
• Est. Priority Date: 06/28/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Drumm, Anthony D., Todd, Kenneth W., Itskin, Randall C.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/212,529
• Time in Patent Office: 1,001 Days
• Field of Search: 264/488, 264/489, 264/490, 264/491, 264/300
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A computer program is disclosed providing a sequence of automated logic synthesis routines having three phases. Phase I identifies an estimated critical path by assuming optimum allocation within a "best-fit" preliminary assignment of the technology to a technology-independent model, and optimizes the estimated model for speed. Phase II provides a technology-legal model, and ends by calculating the actual timing provided by the technology-legal model. Phase III uses self-limiting routines, and routines that are unlikely to produce technology violations, to fine tune the production and performance characteristics of the legal model.

Claims

1. A method of logic synthesis that avoids producing the uncorrectable timing problems that are encountered when rules for a given technology are assigned to a technology independent logic model, said given technology having a prescribed set of available functional logic blocks, said method comprising the steps of:

(a) identifying logic blocks in the model that are not available in said given technology;

(b) estimating the timing characteristics of said logic blocks that are not available in said given technology based upon the characteristics of similar logic blocks that are available, thereby providing a preliminary model;

(c) calculating the timing values for the preliminary model using fan-out values that are limited to a predetermined maximum load;

(d) applying timing correction routines to the critical path in the preliminary model, thereby providing an estimated model; and

(e) correcting violations of the rules of said given technology in the estimated model, thereby providing a technology-legal model.

2. The method of claim 1 further comprising the step of locally recalculating slacks in the model after a correction is made.

3. The method of claim 1 further comprising the step of providing adjusted average delay times for selected blocks in the model for use in timing value calculations.

4. The method of claim 1 further comprising the step of forcing a timing correction routine to ignore selected eligible blocks in the model when making timing corrections in the model.

5. Apparatus for producing logic synthesis by assigning rules for a given technology to a technology-independent logic model while avoiding uncorrectable timing problems, said given technology having a prescribed set of available functional logic blocks, said apparatus comprising:

(a) means for identifying logic blocks in the model that are not available in said given technology;

(b) means for estimating the timing characteristics of said logic blocks that are not available in said given technology based upon the characteristics of similar logic blocks that are available, thereby providing a preliminary model;

(c) means for calculating the timing values for the preliminary model using fan-out load values that are limited to a predetermined maximum load;

(d) means for applying timing correction routines to the critical path in the preliminary model, thereby providing an estimated model; and

(e) means for correcting violations of the rules of said given technology in the estimated model, thereby providing a technology-legal model.

6. The apparatus of claim 5 further comprising means for locally recalculating slacks in the model after a correction is made.

7. The apparatus of claim 5 further comprising means for providing adjusted average delay times for selected blocks in the model for use in timing value calculations.

8. The apparatus of claim 5 further comprising means for forcing a timing correction routine to ignore selected eligible blocks in the model when making timing corrections in the model.