Unit circuit for constructing a neural network and a semiconductor integrated circuit having the same

• US 5,004,932 A
• Filed: 06/27/1989
• Issued: 04/02/1991
• Est. Priority Date: 07/01/1988
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nejime, Yoshito
• Primary Examiner(s): Hudspeth, David
• Application Number:
  US07/373,261
• Time in Patent Office: 644 Days
• Field of Search: 307/201, 307/446, 307/464, 307/465, 307/467, 307/494, 307/495, 307/497, 307/498, 307/296.7, 364/513, 364/807, 341/154
• US Class Current: 326/36
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

A semiconductor integrated circuit for constructing a neural network model, comprising a differential amplifier which includes one output terminal and two input terminals, an excitatory synapse circuit which is connected to the noninverting input terminal of said differential amplifier, and an inhibitory synapse circuit which is connected to the inverting input terminal of said differential amplifier, wherein each of said excitatory and inhibitory synapse circuits includes a plurality of current switches, regulated current source ciruits which are equal in number to said current switches and which determine currents to flow through said current switches, and one load resistor which is connected to all of said current switches, input terminals of said each synapse circuit being constructed of terminals which turn "on" and "off" the respective current switches and to which external inputs or outputs of another neural circuit are connected, said each regulated current source circuit being constructed of a circuit whose current value can be increased or decreased by a voltage externally applied separately and as to which a value of the voltage for increasing or decreasing the current value corresponds to a synaptic weight.

Claims

1. A unit circuit for constructing a neural network comprising:

a differential amplifier which includes an output terminal, an inverting input terminal and a noninverting input terminal;

an excitory synapse circuit which is connected to the noninverting input terminal of said differential amplifier; and

an inhibitory synapse circuit which is connected to the inverting input terminal of said differential amplifier,

wherein each of said excitory and inhibitory synapse circuits includes a plurality of current switches, a regulated current source array which is configured of regulated current source circuits being equal in number to the number of said current switches, said regulated current source circuits determining values of currents that flow through said current switches, and includes one load resistor which is connected to all of said current switches, and

wherein input terminals of each synapse circuit are responsive to inputs which turn "on" and "off" the respective current switches and to which input terminals external inputs or outputs of other unit circuits are applied, said regulated current source circuits having current values which can be respectively altered by voltages externally applied independently of one another.

2. A unit circuit according to claim 1, wherein each one of said regulated current source circuits includes a MOS transistor with a control gate and a floating gate and a resistor, whereby in response to a pulse voltage being impressed on the control gate of said MOS transistor control of the value of current which flows through the corresponding regulated current source circuit is effected.

3. A unit circuit according to claim 1, wherein in said regulated current source array, a summation current corresponding to the sum of currents flowing through all of said regulated current source circuits included therein is held constant by a further single regulated current source commonly coupled therewith.

5. A unit circuit according to claim 1, wherein each one of said current switches includes one pair of transistors and resistors which are connected in series with emitters of the respective transistors, and wherein said resistors includes resistors whose resistances can be controllably altered externally.

6. A unit circuit according to claim 5, wherein in said current switches, said resistors include pinch resistors having externally applied thereto a controllable voltage potential.

4. A unit circuit for constructing a neural network comprising:

a differential amplifier which includes an output terminal, an inverting input terminal and a noninverting input terminal;

an excitory synapse circuit which is connected to the noninverting input terminal of said differential amplifier; and

an inhibitory synapse circuit which is connected to the inverting input terminal of said differential amplifier,

wherein each of said excitory and inhibitory synapse circuits includes a plurality of current switches, a regulated current source array which is configured of regulated current source circuits being equal in number to the number of said current switches, said regulated current source circuits determining values of currents that flow through said current switches, and includes one load resistor which is connected to all of said current switches,

wherein input terminals of each synapse circuit are responsive to inputs which turn "on" and "off" the respective current switches and to which input terminals external inputs or outputs of other unit circuits are applied, and

wherein said regulated current source array includes a plurality of transistors whose emitter areas differ in accordance with values of currents to be respectively flowing therethrough.

7. A unit circuit for constructing a neural circuit comprising:

a current comparison circuit which includes an output terminal, an inverting input terminal and a noninverting input terminal;

an excitatory synapse circuit which is connected in series with the noninverting input terminal of said current comparison circuit an which includes at least one current output type digital-to-analog (D/A) converter; and

an inhibitory synapse circuit which is connected in series with the inverting input terminal of said current comparison circuit and which includes at least one current output type D/A converter, wherein each of said excitatory and inhibitory synapse circuits includes a plurality of input terminals which have weights, respectively, and to which input terminals external outputs of other unit circuits are applied in any desired combination of said plurality of input terminals.

8. A unit circuit according to claim 7, wherein each synapse circuit includes a D/A converter comprised of a plurality of interconnected digital-to-analog converting circuit sets each of which is comprised of first and second resistors of relative resistance R and 2R, respectively, and a current switch circuit formed of bipolar transistors.

9. A unit circuit according to claim 8, wherein each converting circuit set is correspondingly associated with a respective one of a plurality of binary bit inputs applied at a corresponding bipolar transistor base input terminal of a first bipolar transistor of a differentially-coupled pair of bipolar transistors, the other one of said pair of bipolar transistors having base input terminals commonly-biased with a reference potential, and wherein said second resistor has one end coupled to a common emitter connection of a pair of corresponding differentially-coupled transistors, another other end of said second resistor being connected to a first end of a corresponding first resistor having another end coupled to a common connection of the first and second resistors of another converting circuit set.

10. A unit circuit according to claim 9, wherein said bipolar transistors are PNP transistors.

11. A unit circuit for constructing a neural network comprising:

a differential amplifier which includes an output terminal, an inverting input terminal and a noninverting input terminal;

an excitory synapse circuit which is coupled to the noninverting input terminal of said differential amplifier; and

an inhibitory synapse circuit which is coupled to the inverting input terminal of said differential amplifier,

wherein each of said excitatory and inhibitory synapse circuits includes a plurality of current switches, a regulated current source array which is configured of regulated current source circuits being equal in number to the number of said current switches, said regulated current source circuits determining values of currents that flow through said current switches, and includes one load resistor which is connected to all of said current switches,

wherein input terminals of each synapse circuit are responsive to inputs which turn "on" and "off" the respective current switches and to which input terminals external inputs or outputs of other unit circuits are applied, and

wherein said plurality of current switches have respective saturation functions which are exerted on signals applied on respective input terminals of each of said excitatory and inhibitory synapse circuits.

12. A semiconductor integrated circuit having unit circuits constructing a neural network, each one of said unit circuits comprising:

a differential amplifier which includes an output terminal, an inverting input terminal and a noninverting input terminal;

an excitory synapse circuit which is connected to the noninverting input terminal of said differential amplifier; and

an inhibitory synapse circuit which is connected to the inverting input terminal of said differential amplifier,

wherein each of said excitory and inhibitory synapse circuits includes a plurality of current switches, a regulated current source array which is configured of regulated current source circuits being equal in number to the number of said current switches, said regulated current source circuits determining values of currents that flow through said current switches, and includes one load resistor which is connected to all of said current switches, and

wherein input terminals of each synapse circuit are responsive to inputs which turn "on" and "off" the respective current switches and to which input terminals external inputs or outputs of other unit circuits are applied, said regulated current source circuits having current values which can be respectively altered by voltages externally applied independently of one another.

13. A semiconductor integrated circuit according to claim 12, wherein each one of said regulated current source circuits includes a non-volatile MOS transistor, having a control terminal, and a current conducting channel in series connection with a respective resistor whereby in response to a pulse voltage applied on said control terminal control of the value of current flow through the corresponding regulated current source circuit is effected.

14. A semiconductor integrated circuit according to claim 12, wherein in said regulated current source array, a summation current corresponding to the sum of currents flowing through all of said regulated current source circuits included therein is held constant by a further single regulated current source commonly coupled therewith.

15. A semiconductor integrated circuit having unit circuits constructing a neural network, each one of said unit circuits comprising:

a differential amplifier which includes an output terminal, an inverting input terminal and a noninverting input terminal;

an excitory synapse circuit which is connected to the noninverting input terminal of said differential amplifier; and

an inhibitory synapse circuit which is connected to the inverting input terminal of said differential amplifier,

wherein each of said excitory and inhibitory synapse circuits includes a plurality of current switches, a regulated current source array which is configured of regulated current source circuits being equal in number to the number of said current switches, said regulated current source circuits determining values of currents that flow through said current switches, and includes one load resistor which is connected to all of said current switches, and

wherein input terminals of each synapse circuit are responsive to inputs which turn "on" and "off" the respective current switches and to which input terminals external inputs or outputs of other unit circuits are applied, and

wherein said regulated current source array includes a plurality of transistors whose emitter areas differ in accordance with values of currents to be respectively flowing therethrough.

16. A semiconductor integrated circuit having unit circuits constructing a neural network, each one of said unit circuits comprising:

a current comparison circuit which includes an output terminal, an inverting input terminal and a noninverting input terminal;

an excitatory synapse circuit which is connected in series with the noninverting input terminal of said current comparison circuit an which includes at least one current output type digital-to-analog (D/A) converter; and

an inhibitory synapse circuit which is connected in series with the inverting input terminal of said current comparison circuit and which includes at least one current output type D/A converter,

wherein each of said excitatory and inhibitory synapse circuits includes a plurality of input terminals which have weights, respectively, and to which input terminals external outputs of other unit circuits are applied in any desired combination of said plurality of input terminals.

17. A semiconductor integrated circuit according to claim 16, wherein each synapse circuit includes a D/A converter comprised of a plurality of interconnected digital-to-analog converting circuit sets each of which is comprised of first and second resistors of relative resistances R and 2R, respectively, and a current switch circuit formed of bipolar transistors.

18. A semiconductor integrated circuit according to claim 17, wherein each converting circuit set is correspondingly associated with a respective one of a plurality of binary bit inputs applied at a corresponding bipolar transistor base input terminal of a first bipolar transistor of a differentially coupled pair of bipolar transistors, the other one of said pair of bipolar transistors having base input terminals commonly-biased with a reference potential, and wherein said second resistor has one end coupled to a common emitter connection of a pair of corresponding differentially-coupled transistors, another end of said second resistor being connected to a first end of a corresponding first resistor having another end coupled to a common connection of the first and second resistor of another converting circuit set.

19. A semiconductor integrated circuit according to claim 18, wherein said bipolar transistors are PNP transistors.