Method and apparatus for modifying micro-instructions using a macro-instruction pipeline

• US 5,005,118 A
• Filed: 04/10/1987
• Issued: 04/02/1991
• Est. Priority Date: 04/10/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Lenoski, Daniel E.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Chan, Emily Y.
• Application Number:
  US07/036,726
• Time in Patent Office: 1,453 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/200, 364/900
• US Class Current: 712/213
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A method and mechanism operate for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

Claims

1. An apparatus for executing instructions in a controller having at least first and second function units which each include an arithmetic logic unit, comprising:

a macro-instruction register;

a next macro-instruction register coupled to said macro-instruction register;

first logic means, coupled to one of said instruction registers, for generating control signals to concurrently execute, during a single clock cycle, first and second operations in said first and second function units, respectively, said first operation being used to carry out a first macro-instruction in said first macro-instruction register and said second operation being performed to carry out a next macro-instruction, and for using the result of said second operation during the execution of said next macro-instruction if said next macro-instruction has a number of operations less than a predetermined number and otherwise re-executing said second operation;

second logic means for decoding said next macro-instruction to determine whether less than said predetermined number of operations are required;

wherein one of said first and second operations is a memory access operation and said first logic means includes

a first logic stage for providing access to a memory,

a second logic stage having a first arithmetic logic unit for performing arithmetic operations on data provided from at least one of said first and next macro-instructions and said memory, and

a third logic stage having a second arithmetic logic unit for performing arithmetic operations on data provided from at least one of said first and next macro-instructions and said memory, at least two of said first, second and third logic stages being concurrently operated for a portion of said first and next macro-instructions.