Remote control

• US 5,005,187 A
• Filed: 03/23/1989
• Issued: 04/02/1991
• Est. Priority Date: 03/25/1988
• Status: Expired due to Term

• Current Assignee: PICO Electronic Limited
• Original Assignee: PICO Electronic Limited
• Inventors: Thompson, David R.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US07/327,975
• Time in Patent Office: 740 Days
• Field of Search: 375/78, 375/88, 375/92, 375/94, 375/93, 340/310 R, 340/310 A, 329/300, 329/311, 328/173, 379/66
• US Class Current: 375/340
• CPC Class Codes: G08B 29/26 by updating and storing reference thresholds
• CPC Class Codes: H02J 13/00009 using pulsed signals
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: Y02E 60/00 Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
• CPC Class Codes: Y04S 40/121 using the power network as support for the transmission

Abstract

In the field of powerline carrier transmission and reception for remote control, a slave receiver counts cycles of carrier in a time window near to a zero-crossing of the power main. The receiver is implemented using discrete components (1,2,3) and a microprocessor. The discrete components form an input filter (1), a limiting preamplifier (2), a demodulator and noise filter (3) and, along with the microprocessor, a system (4) to detect the zero-crossing points. A capacitor is charged and discharged, depending upon the rate of occurrence of carrier cycles to produce a binary signal dependent on the digital value present on the carrier. By measuring the length of time the binary signal is in one of its states in said time window, the microprocessor determines whether the signal resulted from noise or not.

Claims

1. A slave receiver for detecting commands in the form of digital signals modulated on a cyclic carrier, the receiver comprising:

(a) an input for said carrier;

(b) capacitive means;

(c) first charging means coupling the input to said capacitive means for causing cycles of the carrier to charge the capacitive means beyond a predetermined level of charge when the carrier cycles exist above a given frequency and for at least a first given time;

(d) second charging means for applying charge to the capacitive means in the opposite direction so that, when the predetermined level of charge has been exceeded and there is a subsequent gap in the carrier cycles of a second given time, the charge falls below said predetermined level, and when carrier cycles are subsequently restored said predetermined level of charge is reached after a time directly related to the length of such gap;

(e) switching means coupled to the capacitive means to produce a binary signal corresponding to the existence of said predetermined level of charge;

(f) means for defining time windows; and

(g) means coupled to the switching means for processing said binary signal within said time windows to determine therefrom digital values dependent upon states of the binary signal within said windows.

2. A slave receiver as claimed in claim 1, wherein the output stage of the switching means is such that its output level is directly related to the peak-to-peak level of the carrier up to a given limit.

3. A slave receiver as claimed in claim 1 for coupling to an alternating voltage power main, having points at which the alternating voltage passes through zero, to receive digital signals therefrom conveyed by a carrier modulated on the power main, wherein said windows are synchronised with the said points of the power main.

4. A slave receiver as claimed in claims 1, wherein the processing means is operable to discriminate between noise and digital values in that it comprises means for determining the length of time for which the second state exists in the said windows.

5. A slave receiver for detecting commands in the form of digital signals modulated on a cyclic carrier, the receiver comprising:

(a) an input for said carrier;

(b) capacitive means;

(c) first charging means coupling the input to said capacitive means for causing cycles of the carrier to charge the capacitive means beyond a predetermined level of charge when the carrier cycles exist above a given frequency and for at least a first given time;

(d) second charging means for applying charge to the capacitive means in the opposite direction so that, when the predetermined level of charge has been exceeded and there is a subsequent gap in the carrier cycles of a second given time, the charge falls below said predetermined level, and when carrier cycles are subsequently restored said predetermined level of charge is reached after a time directly related to the length of such gap;

(e) switching means coupled to the capacitive means to produce a binary signal corresponding to the existence of said predetermined level of charge;

(f) means for defining time windows; and

(g) means coupled to the switching means for processing said binary signal within said time windows to determine therefrom digital values dependent upon states of the binary signal within said windows,

wherein said input for said carrier comprises;

(i) an input to receive said signal;

(ii) a current flow path comprising a sequential arrangement of two diodes with the same conducting direction; and

(iii) a first capacitance coupling the input to the junction between said diodes,

said capacitive means comprising a second capacitance connected across diodes, and

the output stage comprising switching means having a control input connected across the second capacitance, so that the state of the switching means is dependent upon the charge of the second capacitance.

6. A slave receiver as claimed in claim 5 wherein resistance is included in said sequential arrangement.

7. A slave receiver as claimed in claim 5, and comprising a pre-amplifier coupling said input to said first capacitance.

8. A slave receiver as claimed in claim 5, and comprising power supply points for the circuit and wherein the switching means, the sequential arrangement and said pre-amplifier are connected between said power supply points.

9. A slave receiver as claimed in claim 5, and further comprising an input stage having an input filter for coupling to the mains to receive therefrom a carrier signal modulated on the mains and a limiter for limiting the peak-to-peak value of the carrier signal as delivered to the input stage.

10. A slave receiver for coupling to a main power to receive digital signals therefrom conveyed by a carrier modulated on the power main, the digital values of a received signal being dependent upon the number of cycles of carrier within windows synchronised with the zero crossings of the power main, the receiver having a demodulator comprising input means for coupling to a power main to extract therefrom a carrier signal of given frequency, limiting means to limit the amplitude of the extracted signal, a capacitive arrangement arranged to be charged and discharged in dependence upon the presence and absence of cycles of the extracted signal and output means arranged to adopt one or other of two states depending upon the level of charge on the capacitive arrangement, the demodulator being such that the output means is in a first state in the absence of any extracted signal and adopts and maintains the second state in the presence of a substantially continuous extracted signal (at said given frequency) for at least a given time, adopting the first state again when gaps in the cycles of the extracted signal exist for more than a given time or when the frequency of the extracted signal is below a second frequency less than the given frequency, thereby to demodulate said carrier signal whilst discriminating against noise signals on the power main.

11. A slave receiver according to claim 10 and including computing means coupled to detect said states and programmed to discriminate between noise and the intended digital values conveyed by the carrier in said window on the basis of the length of time for which said second state exists during the windows.