Method of making an electrostatic silicon accelerometer

• US 5,006,487 A
• Filed: 03/27/1990
• Issued: 04/09/1991
• Est. Priority Date: 07/27/1989
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Stokes, John F.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Holtzman, Laura M.
• Application Number:
  US07/499,756
• Time in Patent Office: 378 Days
• Field of Search: 148/DIG. 12, 437/228, 437/63, 437/66, 437/927, 437/974, 73/517 AV, 73/518, 73/517 R
• US Class Current: 438/52
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 15/131 with electrostatic counterbalancing means
• CPC Class Codes: G01P 2015/0828 the mass being of the paddle type being suspended at one of its longitudinal ends
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 438/924 To facilitate selective etching

Abstract

A solid state accelerometer having an all silicon sensor for measuring accelerational and gravitational forces. The accelerometer measuring system also has associated electronics that include an analog rebalance loop and a digitizer loop.

Claims

1. A method for making a solid state accelerometer, comprising:

depositing a p+ doped layer of epitaxial silicon on a double-sided polished first p- doped silicon wafer;

dry etching a first pattern on the epitaxial silicon to define flexures and a proof mass;

fusion bonding a second p- doped silicon wafer to the p+ doped layer of epitaxial silicon;

thermally oxidizing the exposed surfaces of said first and second p- doped silicon wafers to grow dielectric interlayers to set widths of gaps for the proof mass;

applying an etch resistant material of a second pattern the dielectric interlayers;

anisotropically etching the first and second p- doped wafers to make individual flexures and the proof mass;

removing inner portions of the dielectric interlayers to make the gaps; and

fusion bonding first and second p+ doped silicon stop wafers to the dielectric interlayers of the first and second p- doped silicon wafers, thereby constituting the gaps between the proof mass and the first and second p+doped silicon stop wafers, and sealing the proof mass from volume external to the proof mass.

2. The method of claim 1 further comprising connecting associated electronics to the first and second p+ wafers and to the epitaxial layer, for measuring accelerational or gravitational forces via capacitances of the gaps which are varied by the accelerational or gravitational forces affecting the proof mass, for applying voltages across the proof mass and the first and second p+ doped silicon wafers to counteract with electrostatic forces the accelerational or gravitational forces affecting the proof mass, and for providing indications of the magnitudes of the accelerational or gravitational forces.

3. The method of claim 2 wherein the dielectric interlayers are SiO₂ and SiN₃.

4. The method of claim 3 wherein the proof mass is a diaphragm.

5. The method of claim 3 wherein the proof mass is a pendulum.