Cascaded buck converter circuit with reduced power loss

• US 5,006,782 A
• Filed: 06/15/1989
• Issued: 04/09/1991
• Est. Priority Date: 06/15/1989
• Status: Expired due to Fees

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Pelly, Brian R.
• Primary Examiner(s): Wong, Peter S.
• Application Number:
  US07/366,689
• Time in Patent Office: 663 Days
• Field of Search: 323/224, 323/225, 323/266, 323/267, 323/268, 323/271, 323/282, 323/290, 363/63
• US Class Current: 323/225
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

Two or more buck converter circuits are cascaded in such a manner that the output of one serves as the input to the next, with the input voltage to each succeeding buck converter stage being reduced in magnitude. The total circuit losses are substantially reduced as compared to the losses generated in a single buck converter having the same input voltage range and the same output voltage and output current. Both positive and negative output terminals may be provided for an output stage.

Claims

1. A cascaded buck converter circuit comprising, in combination:

a pair of input terminals for connection to a source of input voltage;

a first and a second switching transistor;

a first and a second diode, a first and a second inductor and a first and a second capacitor;

said pair of input terminals, said first switching transistor, said first inductor and said first capacitor connected in series circuit relation;

said first diode connected in parallel with the series connection of said first inductor and said first capacitor thereby to define a first buck converter stage;

said first capacitor, said second switching transistor, said second inductor and said second capacitor connected in series circuit relation;

said second diode connected in parallel with the series connection of said second inductor and said second capacitor;

the terminals of said second capacitor defining a pair of output terminals for connection to one of an output circuit or to a further buck converter stage;

said first and second switching transistor being comprised respectively of a first and second power MOSFET each with a respective silicon area, the first and second MOSFET transistors being so selected that the total silicon area of said first and second power MOSFETs is substantially less than a silicon area associated with a single buck converter circuit having the same input and output voltages and the same output current as those of said cascaded buck converter circuit.

2. The circuit of claim 1 which includes control circuit means for controlling the switching frequency of said first switching transistor in a manner as to maintain a given voltage across said first capacitor.

3. The circuit of claim 2 which includes control circuit means for operating said second switching transistor at a substantially fixed duty cycle.

4. The circuit of claim 1 wherein the power losses of said circuit are less than the power loss of a single buck converter circuit having the same input and output voltages and the same output current as those of said cascaded circuit.

5. The circuit of claim 3 wherein said source of input voltage varies from less than about 90 to more than about 450 volts and the output voltage at said output terminals is approximately 15 volts.

6. The circuit of claim 5 wherein the power losses of said circuit are less than the power loss of a single buck converter circuit having the same input and output voltages and the same output current as those of said circuit.

9. The cascaded buck converter circuit of claim 1 wherein one of said pair of output terminals is a positive output terminal and is connected to a node located between said second capacitor and said second inductor, and wherein the other of said pair of output terminals is a ground terminal.

10. The cascaded buck converter circuit of claim 6 wherein one of said pair of output terminals is a positive output terminal and is connected to a node located between said second capacitor and said second inductor, and wherein the other of said pair of output terminals is a ground terminal.

11. The cascaded buck converter circuit of claim 9 which further includes a third capacitor connected in series with said second inductor and said second capacitor;

a node between said second and third capacitors connected to said ground terminal;

a negative output terminal;

the side of said third capacitor opposite the side connected to said node being connected to said negative output terminal; and

circuit means coupling said third capacitor to said second switching transistor to permit the charging of said third capacitor.

12. The cascaded buck converter circuit of claim 10 which further includes a third capacitor connected in series with said second inductor and said second capacitor;

a node between said second and third capacitors connected to said ground terminal;

a negative output terminal;

the side of said third capacitor opposite the side connected to said node being connected to said negative output terminal; and

circuit means coupling said third capacitor to said second switching transistor to permit the charging of said third capacitor.

13. The cascaded buck converter of claim 11 wherein said circuit means includes third inductor means connected in series with said second switching transistor and third diode means;

said third inductor means and said third diode means connected in closed series relation with at least said third capacitor.

14. The cascaded buck converter of claim 12 wherein said circuit means includes third inductor means connected in series with said second switching transistor and third diode means;

said third inductor means and said third diode means connected in closed series relation with at least said third capacitor.

7. A cascaded buck converter circuit comprising, in combination:

a first buck converter stage including a first switching transistor means, a first output capacitor and first input terminal means;

a second buck converter stage including a second switching transistor means, a second output capacitor and second input terminal means;

a variable input voltage connected to said first input terminal means, and control means for modifying the duty cycle of said first switching transistor means to maintain a constant voltage across said first output capacitor;

said first output capacitor connected to said second input terminal means;

said second switching transistor means having a duty cycle which maintains a given output voltage across said second capacitor;

said first and second switching transistor means being comprised respectively of a first and second power MOSFET each with a respective silicon area, the first and second MOSFET transistors being so selected that the total silicon area of said first and second power MOSFETs is substantially less than a silicon area associated with a single buck converter circuit having the same input and output voltages and the same output current as those of said cascaded buck converter circuit.

8. The circuit of claim 7 wherein said output voltage across said second capacitor is a constant voltage regardless of changes in said input voltage.

15. A cascaded buck converter circuit, comprising:

positive, negative and ground output terminals;

a pair of input terminals for connection to a source of input voltage;

a first buck converter stage including a first switching transistor means, a first output capacitor and first input terminal means;

a second buck converter stage coupled between said first stage and said output terminals and including a second switching transistor means;

inductor means coupled between said positive output terminal and said second switching transistor; and

first and second output capacitors;

one side of each of said first and second output capacitors connected to said ground terminal;

the other side of said first output capacitor connected to said positive output terminal;

the other side of said second output capacitor connected to said negative output terminal; and

diode means coupled between said inductor means and said first and second capacitor means to permit charging in series with said inductor means of said first output capacitor from said pair of input terminals when said second switching transistor means is on during its duty cycle and to permit current flow to continue through said inductor means and said first and second capacitors when said second switching transistor means is off during its duty cycle;

said first and second switching transistor means being comprised respectively of a first and second power MOSFET each with a respective silicon area, the first and second MOSFET transistors being so selected that the total silicon area of said first and second power MOSFETs is substantially less than a silicon area associated with a single buck converter circuit having the same input and output voltages and the same output current as those of said cascaded buck converter circuit.

16. The buck converter circuit of claim 15 wherein said inductor means comprises first and second inductors connected in respective first and second closed circuits each of which includes said diode means and a respective one of said first and second capacitors.

17. The buck converter circuit of claim 16 wherein said diode means includes first and second diodes connected in said first and second closed circuits, respectively.