Method and apparatus for converting A/D nonlinearities to random noise

• US 5,006,854 A
• Filed: 02/13/1989
• Issued: 04/09/1991
• Est. Priority Date: 02/13/1989
• Status: Expired due to Fees

• Current Assignee: Silicon Systems, Inc. (Texas Instruments, Inc.)
• Original Assignee: Silicon Systems, Inc. (Texas Instruments, Inc.)
• Inventors: Negabahn-Hagh, Mehrdad, White, Bert
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Logan, Sharon D.
• Application Number:
  US07/311,237
• Time in Patent Office: 785 Days
• Field of Search: 341/172, 341/167, 341/166, 341/161, 341/164, 341/165, 341/118
• US Class Current: 341/172
• CPC Class Codes: H03M 1/0673 using random selection of the elements with data-controlled random generator H03M1/0665
• CPC Class Codes: H03M 1/466 using switched capacitors
• CPC Class Codes: H03M 1/806 with equally weighted capacitors which are switched by unary decoded digital signals

Abstract

A method and apparatus for removing the effects of mismatched components in an A/D converter is described. The present invention dynamically rearranges the capacitors of an A/D converter so that physical mismatch is averaged out. In the preferred embodiment of the present invention, an array of equally-sized capacitors is coupled to a switching network. A successive approximation scheme is implemented in which the input signal is coupled through SAR switches to the capacitor array. Each switch is coupled to 2^N-1 capacitors where N is the switch number. For example, in an 8-bit scheme, there are 3 switches with switch 1 coupled to one capacitor, switch 2 coupled to two capacitors, and switch 3 coupled to four capacitors. In this manner, eight levels of capacitance values can be defined. The present invention adds a scramble control code to control the switching array so that the physical capacitors themselves are coupled to different SAR switches at different times. This requires a scramble matrix of switches, which in the present invention requires N×2N switches where N equals the number of bits of control code. In this manner, the effects of any variations in the capacitance ratios is averaged out and converted to noise which can be filtered out of the signal.

Claims

1. A circuit comprising:

a plurality of capacitors, each having a capacitance of approximately C;

a first switch coupled to a first number x of said capacitors;

a second switch coupled to a second number y of said capacitors;

a switching matrix coupled to said plurality of capacitors and to said first and second switches for selectably coupling said plurality of capacitors to each of said first and second switches such that the time-averaged ratio of the amount of time one of said capacitors is coupled to said first switch compared to the amount of time said one of said capacitors is coupled to said second switch is approximately equal to x/y.

2. The circuit of claim 1 wherein said switching matrix is controlled by a control code.

3. The circuit of claim 2 wherein said control code is provided by a digital counter.

4. The circuit of claim 2 wherein said control code is provided by a pseudo random-number generator.

5. The circuit of claim 2 wherein said first and second switches are SAR switches.

6. The circuit of claim 5 wherein said switching matrix comprises a plurality of third switches coupled to said second switch and a plurality of fourth switches coupled to said first switch and said plurality of third switches.

7. The circuit of claim 6 wherein a least significant bit of said control code controls said plurality of fourth switches.

8. A method of reducing the effects of component mismatch in an analog to digital (A/D) converter having a plurality of capacitors each having a capacitance of approximately C, said plurality of capacitors coupled to a plurality of switches, said method comprising the steps of:

defining at least first and second groups of said capacitors, said first group comprising x capacitors and said second group comprising y capacitors;

selectively coupling a first of said switches to said first group and a second of said switches to said second group;

switching each of said plurality of capacitors into said first group or said second group;

controlling said switching of said capacitors such that the time-averaged ratio of the amount of time one of said capacitors is coupled to said first of said switches compared to the amount of time said one of said capacitors is coupled to said second of said switches is approximately equal to x/y.

9. The method of claim 8 wherein said step of switching each of said plurality of capacitors comprises coupling said capacitors through a switching matrix to said switches.

10. The method of claim 9 wherein said switching matrix is controlled by a control code.

11. The method of claim 10 wherein said control code is provided by a digital counter.

12. The method of claim 10 wherein said control code is provided by a pseudo random-number generator.

13. A circuit comprising:

a plurality of impedance elements, each having an impedance which is approximately equal;

a first switch coupled to a first number x of said elements;

a second switch coupled to a second number y of said elements;

a switching matrix coupled to said elements and to said first and second switches for selectably coupling said plurality of impedance elements to each of said first and second switches such that the time-averaged ratio of the amount of time one of said elements is coupled to said first switch compared to the amount of time said one of said elements is coupled to said second switch is approximately equal to x/y.

14. The circuit of claim 13 wherein said switching matrix is controlled by a control code.

15. The circuit of claim 14 wherein said control code is provided by a digital counter.

16. The circuit of claim 14 wherein said control code is provided by a pseudo-random number generator.

17. The circuit of claim 14 wherein said first and second switches are SAR switches.

18. The circuit of claim 17 wherein said switching matrix comprises a plurality of third switches coupled to said second switch and a plurality of fourth switches coupled to said first switch and said plurality of said third switches.

19. The circuit of claim 18 wherein a least significant bit of said control code controls said plurality of fourth switches.

20. The circuit of claim 19 wherein said plurality of elements comprises a plurality of capacitors.

21. A method of switching elements in a circuit having a plurality of impedance elements, each having an impedance which is approximately equal, coupled to a plurality of switches, said method comprising the steps of:

defining at least first and second groups of impedance elements, said first group comprising x impedance elements and said second group comprising y impedance elements;

selectively coupling a first of said switches to said first group and a second of said switches to said second group;

switching each of said plurality of impedance elements into said first group or said second group;

controlling said switching of said impedance elements, such that the time averaged ratio of the amount of time one of said impedance elements is coupled to said first of said switches compared to the amount of time said one of said impedance elements is coupled to said second of said switches is approximately equal to x/y.

22. The method of claim 21 wherein said step of switching each of said plurality of impedance elements comprises coupling said impedance elements through a switching matrix to said switches.

23. The method of claim 22 wherein said switching matrix is controlled by a control code.

24. The method of claim 23 wherein said control code is provided by a digital counter.

25. The method of claim 23 wherein said control code is provided by a pseudo random number generator.

26. A circuit comprising:

a plurality of impedance elements;

a plurality of switches;

a switching matrix coupled to said impedance elements and to said switches for selectively coupling said impedance elements to said switches such that each of said impedance elements is coupled to not more than one of said switches at any instant, but that each of said impedance elements is eventually coupled to each of said switches.

27. The circuit of claim 26 wherein said switching matrix is controlled by a control code.

28. The circuit of claim 27 wherein said control code is provided by a digital counter.

29. The circuit of claim 27 wherein said control code is provided by a pseudo random number generator.

30. The circuit of claim 27 wherein said first and second switches are SAR switches.

31. The circuit of claim 30 wherein said switching matrix comprises a plurality of third switches coupled to said second switch and a plurality of fourth switches coupled to said first switch and said plurality of fourth switches coupled to said first switch and said plurality of said third switches.

32. The circuit of claim 31 wherein a least significant bit of said control code controls said plurality of fourth switches.

33. The circuit of claim 32 wherein said plurality of elements comprises a plurality of capacitors.

34. The circuit of claim 26 wherein a first of said switches is coupled to a first number x of said impedance elements, and a second of said switches is coupled to a second number y of said impedance elements;

said impedance elements coupled to said switches such that the time-averaged ratio of the amount of time any one of said capacitors is coupled to said first switch compared to the amount of time said one of said capacitors is coupled to said second switch is equal to x/y.