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Dram with a vertical capacitor and transistor

  • US 5,006,909 A
  • Filed: 10/30/1989
  • Issued: 04/09/1991
  • Est. Priority Date: 10/30/1989
  • Status: Expired due to Term
First Claim
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1. A memory array formed in a semiconductor substrate having a first conductivity type and a first doping concentration, comprising:

  • a plurality of conductive bit lines;

    a plurality of pillars of monocrystalline semiconductor material extending from the substrate, each having a first layer reaching a first height and which is the first conductivity type and of a second doping concentration which is less than the first doping concentration, a second layer above the first layer reaching a second height and which is a second conductivity type, a third layer above the second layer reaching a third height and which is the first conductivity type, and a fourth layer above the third layer reaching a fourth height and in contact with a corresponding one of the plurality of conductive bit lines;

    a conductive fill insulated from and surrounding the plurality of pillars to a fifth height which is below the second height;

    an insulating layer above the conductive fill and surrounding the plurality of pillars to a sixth height which is below the second height; and

    a plurality of conductive word lines insulated from and at least partially surrounding the third layers of corresponding pillars of the plurality of pillars to a seventh height which is greater than the third height but less than the fourth height.

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