Dram with a vertical capacitor and transistor

• US 5,006,909 A
• Filed: 10/30/1989
• Issued: 04/09/1991
• Est. Priority Date: 10/30/1989
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kosa, Yasunobu
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): MONIN, DONALD L JR
• Application Number:
  US07/429,952
• Time in Patent Office: 526 Days
• Field of Search: 357/23.6, 357/41, 357/52, 357/55
• US Class Current: 257/302
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A dynamic random access memory array is formed using vertical transistors and capacitors. The capacitor for each memory cell has one electrode formed in a lower region of a pillar and a second electrode in a conductive fill surrounding the lower region of the pillar. The transistor of each cell has its source, drain, and channel also formed in a single pillar. The gate of each cell is a conductive layer surrounding the channel. The conductive layer is above and insulated from the conductive fill. The conductive layer is also conveniently the word line which continuously extends from one cell in a particular row to the next cell of that row. Contact to the cell is made to the top of the pillar which is doped to the same type as that of the lower region of the pillar. The areas between the pillars is filled with insulating material but the top of the pillar is exposed. Metal bit lines are thus conveniently formed in contact with the top of the pillar which is the input/output for the cell.

Claims

1. A memory array formed in a semiconductor substrate having a first conductivity type and a first doping concentration, comprising:

a plurality of conductive bit lines;

a plurality of pillars of monocrystalline semiconductor material extending from the substrate, each having a first layer reaching a first height and which is the first conductivity type and of a second doping concentration which is less than the first doping concentration, a second layer above the first layer reaching a second height and which is a second conductivity type, a third layer above the second layer reaching a third height and which is the first conductivity type, and a fourth layer above the third layer reaching a fourth height and in contact with a corresponding one of the plurality of conductive bit lines;

a conductive fill insulated from and surrounding the plurality of pillars to a fifth height which is below the second height;

an insulating layer above the conductive fill and surrounding the plurality of pillars to a sixth height which is below the second height; and

a plurality of conductive word lines insulated from and at least partially surrounding the third layers of corresponding pillars of the plurality of pillars to a seventh height which is greater than the third height but less than the fourth height.

2. The memory of claim 1 wherein the substrate is of the second conductivity type and has a first doping concentration, and wherein each of the plurality of pillars further comprises a fourth layer of the second conductivity type between the first layer and the substrate, said fourth layer being of a second doping concentration.

3. The memory of claim 2 wherein the second doping concentration is less than the first doping concentration.

4. The memory of claim 1 further comprising an insulating fill over the plurality of conductive word lines to a height less than the fourth height.

5. A memory array formed in a semiconductor substrate having a first conductivity type and a first doping concentration, comprising:

a plurality of conductive bit lines;

a plurality of pillars of monocrystalline semiconductor material extending from the substrate, each having a first layer reaching a first height and which is the first conductivity type and of a second doping concentration which is less than the first doping concentration, a second layer above the first layer reaching a second height and which is a second conductivity type, a third layer above the second layer reaching a third height and which is the first conductivity type, and a fourth layer above the third layer reaching a fourth height and in contact with a corresponding one of the plurality of conductive bit lines;

a plurality of first insulating films, each first insulating film surrounding a corresponding one of the plurality of pillars from the substrate to a fourth height, said fourth height being less than said first height;

a conductive fill insulated from and surrounding the plurality of pillars to a fifth height which is below the second height;

an insulating layer above the conductive fill and surrounding the plurality of pillars to a sixth height which is below the second height;

a plurality of second insulating films, each second insulating film surrounding a corresponding pillar from the fifth height to a seventh height which is above the third height but below the fourth height; and

a plurality of conductive word lines insulated from and at least partially surrounding the third layers of corresponding pillars of the plurality of pillars to the seventh height.

6. The memory of claim 5 wherein the substrate is of the second conductivity type and has a first doping concentration, and wherein each of the plurality of pillars further comprises a fourth layer of the second conductivity type between the first layer and the substrate, said fourth layer being of a second doping concentration.

7. The memory of claim 6 wherein the second doping concentration is less than the first doping concentration.

8. The memory of claim 5 further comprising an insulating fill over the plurality of conductive word lines to a height less than the fourth height.

9. A memory cell formed on a semiconductor substrate, comprising:

a pillar of monocrystalline semiconductor material extending from the substrate having a first layer reaching a first height and which is the first conductivity type and of a second doping concentration which is less than the first doping concentration, a second layer above the first layer reaching a second height and which is a second conductivity type, a third layer above the second layer reaching a third height and which is the first conductivity type, and a fourth layer above the third layer reaching a fourth height;

an insulating film surrounding the pillar from the substrate to a fifth height, said fifth height being less than said second height;

a conductive fill surrounding the pillar to a sixth height which is below the fifth height;

an insulating layer above the conductive fill and surrounding the pillar to the fifth height;

a second insulating film surrounding the pillar from the fifth height to a seventh height which is above the third height but below the fourth height; and

a conductive word line at least partially surrounding the third layer of the pillar to an eighth height which is greater than the third height but less than the seventh height.

10. The memory of claim 9 wherein the substrate is of the second conductivity type and has a first doping concentration the pillar further comprises a fourth layer of the second conductivity type between the first layer and the substrate, said fourth layer being of a second doping concentration.

11. The memory of claim 10 wherein the second doping concentration is less than the first doping concentration.

12. The memory of claim 9 further comprising an insulating fill over the plurality of conductive word lines to a height less than the fourth height.