Digital to analog converter using pulse width modulator for independently setting edge position

• US 5,008,675 A
• Filed: 09/29/1989
• Issued: 04/16/1991
• Est. Priority Date: 09/29/1988
• Status: Expired due to Term

• Current Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Original Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Inventors: Toyomaki, Kazuya
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US07/414,278
• Time in Patent Office: 564 Days
• Field of Search: 341/143, 341/144, 341/152, 375/22, 329/312, 328/119, 328/164
• US Class Current: 341/152
• CPC Class Codes: H03M 1/068 the original and additional components or elements being complementary to each other, e.g. CMOS
• CPC Class Codes: H03M 1/822 using pulse width modulation

Abstract

A PWM type D/A converter having a first PWM converter, a second PWM converter and an analog adder. The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered input signal are designated as odd/even numbered reference timing points. The first PWM converter receive the digital input signal to output signal whose rising/falling timing point is set at the earlier/later timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal. The second PWM converter receives the digital input signal to output signal whose rising/falling timing point is set at the later timing, the larger the value of the even/odd numbered input signal relative to the even/odd numbered reference timing point and the pulse width is determined by the value of the even numbered input signal and the next odd numbered input signal. In another aspect the second PWM converter receives the digital input signal to output signal whose rising/falling timing point is at the later the timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by complementary values of the odd numbered input signal and the next even numbered input signal.

Claims

1. A PWM type D/A converter wherein digital input signals supplied to the converter at each predetermined input sample period are designated as odd and even numbered input signals alternately in the order of input, the reference timing point for outputting an odd numbered input signal is designated as an odd numbered reference timing point, and the reference timing point for outputting an even number is designated as an even numbered reference timing point, said PWM type D/A converter comprising:

a first PWM converter receiving said digital input signal for outputting an output signal (A) wherein the timing point when said output signal (A) rises from the low level to the high level is set at the earlier the timing, the larger the value of the odd numbered input signal relative to the odd numbered reference timing point, and the timing point when said output signal (A) falls from the high level to the low level is set at the later the timing, the larger the value of the even numbered input signal relative to the even numbered reference timing point, and wherein the pulse width from the rising point to the falling point of said output signal (A) is determined by the values of the odd numbered input signal and the next even numbered input signal;

a second PWM converter receiving said digital input signal for outputting an output signal (B) wherein the timing point when said output signal (B) falls from the high level to the low level is set at the later the timing, the larger the value of the odd numbered input signal relative to the odd numbered reference timing point, and the timing when said output signal (B) rises from the low level to the high level is set at the earlier the timing, the larger the value of the even numbered input signal relative to the even numbered reference timing point, and wherein the pulse width from the rising point to the falling point of said output signal (B) is determined by the values of the even numbered input signal and the next odd numbered input signal; and

an analog adder for adding together said output signal (A) from said first PWM converter and said output signal (B) from said second PWM converter to output a sum signal (A+B);

wherein an analog signal corresponding to said digital input signal is outputted from said analog adder.

2. A PWM type D/A converter wherein digital input signals supplied to the converter at each predetermined input sample period are designated as odd and even numbered input signals alternately in the order of input, the reference timing point for outputting an odd numbered input signal is designated as an odd numbered reference timing point, and the reference timing point for outputting an even number is designated as an even numbered reference timing point, said PWM type D/A converter comprising:

a first PWM converter receiving said digital input signal for outputting an output signal (A) wherein the timing point when said output signal (A) rises from the low level to the high level is set at the earlier the timing, the larger the value of the odd numbered input signal relative to the odd numbered reference timing point, and the timing point when said output signal (A) falls from the high level to the low level is set at the later the timing, the larger the value of the even numbered input signal relative to the even numbered reference timing point, and wherein the pulse width from the rising point to the falling point of said output signal (A) is determined by the values of the odd numbered input signal and the next even numbered input signal;

a second PWM converter receiving said digital input signal for outputting an output signal (C) wherein the timing point when said output signal (C) rises from the low level to the high level is set at the later the timing, the larger the value of the odd numbered input signal relative to the odd numbered reference timing point, and the timing when said output signal (C) falls from the high level to the low level is set at the earlier the timing, the larger the value of the even numbered input signal relative to the even numbered reference timing point, and wherein the pulse width from the rising point to the falling point of said output signal (C) is determined by a complementary values of the values of the odd numbered input signal and the next even numbered input signal; and

an analog subtracter for subtracting from each other said output signal (A) from said first PWM converter and said output signal (C) from said second PWM converter to output a difference signal (A-C) or (C-A);

wherein an analog signal corresponding to said digital input signal is outputted from said analog subtracter.