Dual layer surface gate JFET having enhanced gate-channel breakdown voltage

• US 5,008,719 A
• Filed: 10/20/1989
• Issued: 04/16/1991
• Est. Priority Date: 10/20/1989
• Status: Expired due to Term

• Current Assignee: Cordis Corporation (Cardinal Health, Inc.), Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Schrantz, Gregory A.
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US07/424,917
• Time in Patent Office: 543 Days
• Field of Search: 357/22 D, 357/22 R, 357/52, 357/52 D, 357/20, 357/22 B, 357/22 C, 357/22 G, 357/22 H, 357/49
• US Class Current: 257/261
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: Y10S 257/906 Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

Abstract

Radiation insensitivity and breakdown voltage characteristics of a dual region top gate JFET are improved by a top gate structure in which the entirety of the lower concentration region of the top gate is separated from the oxide/silicon interface by the top surface high impurity concentration region. The dual region top gate extends from the substrate/insulator interface to a channel region beneath the top surface of the JFET substrate and extends laterally to bridge the source and drain regions. The lateral extent of the dual region top gate may be delimited by barrier regions, respectively separating the top gate regions from the source and drain regions. The barrier regions extend from the substrate/oxide interface to the channel and may comprise dielectric material or a combination of dielectric material and doped semiconductor material.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type having a first surface;

first and second semiconductor regions of a second conductivity type, opposite to said first conductivity type, respectively disposed in first and second spaced-apart surface portions of said substrate;

a third, channel, semiconductor region of said second conductivity type, disposed beneath a third surface portion of said substrate and bridging said first and second semiconductor regions; and

a fourth, gate, semiconductor region of said first conductivity type extending from said third surface portion of said substrate, bridging said first and second semiconductor regions and so as to be contiguous with said third semiconductor region, said fourth region containing a fifth semiconductor region of a first impurity concentration, extending from said third surface portion of said substrate to a sixth semiconductor region of a second impurity concentration, lower than said first impurity concentration, said sixth region being contiguous with said third region and being spaced apart from said third surface portion of said substrate.

2. A semiconductor device according to claim 1, further comprising an insulator layer disposed on said third surface portion of said substrate.

3. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type having a first surface;

first and second semiconductor regions of a second conductivity type, opposite to said first conductivity type, respectively disposed in first and second spaced-apart surface portions of said substrate;

a third, channel, semiconductor region of said second conductivity type, disposed beneath a third surface portion of said substrate and bridging said first and second semiconductor regions; and

a fourth surface gate region of said first conductivity type, extending from said third surface portion of said substrate, laterally between said first and second regions, so as to be contiguous with said channel region, said surface gate region including a fifth semiconductor region of a first impurity concentration extending from said third surface portion of said substrate to a sixth semiconductor region of a second impurity concentration, lower than said first impurity concentration, said sixth region being contiguous with said channel region, and wherein the entirety of said laterally extending sixth region is spaced apart from said first surface of said substrate.

4. A semiconductor device according to claim 3, further comprising a an insulator layer disposed on said third surface portion of said substrate.

5. A semiconductor region according to claim 3, wherein each of said fifth and sixth regions overlaps said first and second regions.

6. A semiconductor region according to claim 5, further including seventh and eighth semiconductor regions of said second conductivity type, respectively disposed in said first and second semiconductor regions, said seventh and eighth regions having an impurity concentration greater than that of said first and second regions.

7. A semiconductor region according to claim 6, wherein each of said fifth and sixth regions is separated from said seventh and eighth regions by semiconductor material of said first and second regions, respectively, therebetween.

8. A semiconductor region according to claim 7, wherein said fifth semiconductor region is spaced apart from said seventh and eighth regions by a distance greater than the separation between said sixth semiconductor region and said seventh and eighth regions.

9. A semiconductor region according to claim 3, further including first and second barrier regions, respectively separating said surface gate region from each of said first and second semiconductor regions.

10. A semiconductor region according to claim 9, wherein said barrier regions comprise insulation material.

11. A semiconductor region according to claim 9,.wherein said barrier regions comprise insulation material and doped semiconductor material.

12. A semiconductor region according to claim 9, further including ninth and tenth semiconductor regions of said second conductivity type, disposed in said channel region adjacent to said first and second barrier regions, respectively, said ninth and tenth regions having an impurity concentration higher than that of said channel region.

13. A semiconductor region according to claim 12, wherein said barrier regions comprise insulation material surrounding doped semiconductor material of said first conductivity type.

14. A semiconductor region according to claim 3, further including first and second barrier regions, respectively extending from said first surface of said substrate to said channel region and laterally separating said surface gate region from each of said first and second semiconductor regions.

15. A semiconductor region according to claim 14, wherein each of said first and second barrier regions is comprised of dielectric material.

16. A semiconductor region according to claim 15, further including ninth and tenth semiconductor regions of said second conductivity type, disposed in said channel region adjacent to said first and second barrier regions, respectively, said ninth and tenth regions having an impurity concentration higher than that of said channel region.

17. A semiconductor region according to claim 14, wherein said barrier regions comprise insulation material surrounding doped semiconductor material of said first conductivity type.