Plural polygon source pattern for MOSFET

• US 5,008,725 A
• Filed: 12/23/1988
• Issued: 04/16/1991
• Est. Priority Date: 05/14/1979
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lidow, Alexander, Herman, Thomas, Rumennik, Vladimir
• Primary Examiner(s): Wimer, Michael C.
• Assistant Examiner(s): Brown, Peter Toby
• Application Number:
  US07/291,423
• Time in Patent Office: 844 Days
• Field of Search: 357/23 VD, 357/20, 357/45, 357/86, 357/23.4
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A high power MOSFET has a plurality of closely packed polygonal sources spaced from one another on one surface of a semiconductor body. An elongated gate electrode is exposed in the spacing between the polygonal sources and cooperates with two channels, one for each adjacent source electrode, to control conduction from the source electrode through the channel and them to a drain electrode on the opposite surface of the semiconductor body. The conductive region adjacent the channel and between adjacent sources is relatively highly conductive in the section of the channel adjacent to the surface containing the sources. The polygonal shaped source members are preferably hexagonal so that the distances between adjacent sources is relatively constant throughout the device. Each polygonal region has a relatively deep central portion and a shallow outer shelf portion. The shelf portion generally underlies an annular source region. The deep central portion underlies an aluminum conductive electrode and is sufficiently deep that it will not be fully penetrated by aluminum spiking.

Claims

1. A high power MOSFET device having more than 1000 parallel-connected individual FET devices closely packed into a relatively small area comprising:

a thin wafer of semiconductor material having first and second spaced, parallel planar surfaces;

at least a first portion of the thickness of said wafer which extends from said first planar surface consisting of an epitaxially deposited region of a first conductivity type;

a plurality of symmetrically disposed laterally distributed hexagonal base regions each having a second conductivity type formed in said epitaxially deposited region and extending for a given depth beneath said first planar surface;

said hexagonal base regions spaced at said first surface from surrounding ones by a symmetric hexagonal lattice of semiconductor material of said first conductivity type;

each side of each of said hexagonal base regions being parallel to an adjacent side of another of said hexagonal base regions;

a hexagonal annular source region of said first conductivity type formed in an outer peripheral region of each of said hexagonal base regions and extending downwardly from said first planar surface to a depth less than the depth of said base regions;

an outer rim of each of said annular source regions being radially inwardly spaced from an outer periphery of its respective hexagonal base region to form an annular channel between each of said outer rims of said annular source regions and said symmetric hexagonal lattice of semiconductor material of said first portion of said wafer;

a common source electrode formed on said first planar surface and connected to a plurality of said annular source regions and to interiorly adjacent surface areas of their said respective hexagonal base regions;

a drain electrode connected to said second planar surface of said wafer;

an insulation layer means on said first planar surface and overlying at least said annular channels; and

a polysilicon gate electrode atop said insulation layer means and operable to invert said annular channels.

2. The MOSFET device of claim 1, wherein the material of said lattice of said first conductivity type has a relatively high impurity concentration region compared to the concentration of the remainder of said first portion of said wafer;

said relatively high concentration region having a depth greater than the depth of said source regions and less than the depths of said plurality of base regions.

4. The MOSFET device of claim 1 or 3, wherein each of said base regions occupies a total lateral area having a diameter less than about 1 mil and are spaced from adjacent base regions by about 0.6 mil.

5. The device of claim 1 or 3, wherein said 40M, is an N type conductivity, said base regions are a P type conductivity and said source regions are an N type conductivity.

11. The MOSFET device of claim 1, 3, 35 or 36, wherein each of said base regions has a deepened central region and a shallower outer peripheral region, said deepened central region extending laterally under only a portion of its associated source region.

12. The MOSFET device of claim 11, wherein said deepened central region has a depth of approximately 5 microns and said shallower outer peripheral region has a depth of greater than approximately 1.5 microns.

3. A high power MOSFET device having more than 1000 parallel-connected individual FET devices closely packed into a relatively small area comprising:

a thin wafer of semiconductor material having first and second spaced, parallel planar surfaces;

at least a first portion of the thickness of said wafer which extends from said first planar surface consisting of an epitaxially deposited region of a first conductivity type;

a plurality of symmetrically disposed laterally distributed polygonal base regions each having a second conductivity type formed in said lightly doped region and extending for given depth beneath said first planar semiconductor surface;

said polygonal base regions spaced at said first surface from surrounding ones by a symmetric polygonal lattice of semiconductor material of said first conductivity type;

each side of each of said polygonal base regions being parallel to an adjacent side of another of said polygonal base regions;

a polygonal annular source region of said first conductivity type formed in an outer peripheral region of each of said polygonal base regions and extending downwardly from said first planar surface to a depth less than the depth of said base regions;

an outer rim of each of said annular source regions being radially inwardly spaced from an outer periphery of its respective polygonal base region to form an annular channel between each of said outer rims of said annular source regions and said symmetric polygonal lattice of semiconductor material of said first portion of said wafer;

a common source electrode formed on said first planar surface and connected to a plurality of said annular source regions and to interiorly adjacent surface areas of their said respective polygonal base regions;

a drain electrode connected to said second planar semiconductor surface of said wafer;

an insulation layer means on said first planar surface and overlying at least said annular channels; and

a polysilicon gate electrode atop said insulation layer means and operable to invert said annular channels.

6. The MOSFET device of claim 3, wherein the material of said lattice of said first conductivity type has a relatively high impurity concentration region compared to the concentration of the remainder of said first portion of said wafer;

said relatively high concentration region having a depth greater than the depth of said source regions and less than the depths of said plurality of base regions.

7. A vertical conduction high power MOSFET device exhibiting relatively low on-resistance and relatively high breakdown voltage;

said device comprising;

a wafer of semiconductor material having planar first and second opposing semiconductor surfaces;

said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of a first conductivity type;

a plurality of highly packed, equally spaced symmetrically disposed identical polygonal base regions of a second conductivity type formed in said wafer, each extending from said first planar semiconductor surface to a first depth beneath said first planar semiconductor surface;

said polygonal base regions spaced from surrounding ones by a symmetric polygonal lattice of semiconductor material of said first conductivity type;

the space between adjacent ones of said polygonal base regions defining a common conduction region of said first conductivity type extending downwardly from said first planar semiconductor surface;

a respective polygonal annular source region of said first conductivity type formed within each of said polygonal base regions and extending downwardly from said first planar semiconductor surface to a depth less than said first depth;

each of said polygonal annular source regions being laterally spaced along said first planar semiconductor surface from the facing respective edges of said common conduction region thereby to define respective coplanar annular channel regions along said first planar semiconductor surface between the polygonal sides of each of said polygonal annular source regions and said common conduction region;

a common source electrode means connected to said polygonal annular source regions and their respective base regions;

gate insulation layer means on said first planar semiconductor surface, disposed at least on said coplanar channel regions;

gate electrode means on said gate insulation layer means and overlying said coplanar channel regions;

a drain conductive region remote from said common conduction region and separated therefrom by said relatively lightly doped major body portion and extending to said second semiconductor surface; and

a drain electrode coupled to said drain conductive region.

9. The MOSFET device of claims 7 or 8 wherein said common conduction region is relatively highly doped, compared to said relatively lightly doped major body portion and extends downwardly from said first planar semiconductor surface to a depth greater than the depth of said source regions, whereby resistance to current flow at the boundaries between said channel regions and said common conduction region and between said common conduction region and said relatively lightly doped major body portion is reduced without reducing breakdown voltage.

10. The MOSFET device of claim 9, wherein the depth of said common conduction region is less than said first depth of said base regions.

14. The device of claim 7 or 8, wherein said lightly doped wafer portion is an N type conductivity, said base regions are a P type conductivity and said source regions are an N type conductivity.

8. A high power MOSFET device exhibiting relatively low on-resistance and relatively high breakdown voltage;

said device comprising;

a wafer of semiconductor material having planar first and second opposing semiconductor surfaces;

said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of a first conductivity type;

at least first and second spaced base regions of a second conductivity type formed in said wafer and extending downwardly from said first planar semiconductor surface to a first depth beneath said first planar semiconductor surface;

the space between said at least first and second spaced base regions defining a common conduction region of a first conductivity type at a given first planar semiconductor surface location;

said common conduction region extending downwardly from said first planar semiconductor surface;

first and second annular source regions of said first conductivity type formed in said first and second spaced base regions respectively at said first planar semiconductor surface locations to a depth less than said first depth;

said first and second annular source regions being laterally spaced along said first planar semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first planar semiconductor surface between each pair of said first and second annular source regions, respectively, and said common conduction region;

each of said first and second channel regions being coplanar with one another;

a common source electrode means connected to said first and second annular source regions and their respective first and second base regions;

gate insulation layer means on said first planar semiconductor surface, disposed at least on said first and second channel regions;

gate electrode means on said gate insulation layer means and overlying said first and second channel regions;

a drain conductive region remote from said common conduction region and separated therefrom by said relatively lightly doped major body portion and extending to said second semiconductor surface;

a drain electrode coupled to said drain conductive region; and

each of said at least first and second spaced base regions having a polygonal configuration;

each of said first and second annular source regions having a polygonal configuration conforming to that of their respective base region.

13. The device of claim 32, 35 or 36, wherein there are in excess of about 1000 source regions each having a width of about 1 mil.