Computer and telephone apparatus with user friendly computer interface integrity features

• US 5,008,927 A
• Filed: 10/21/1988
• Issued: 04/16/1991
• Est. Priority Date: 05/05/1988
• Status: Expired due to Term

• Current Assignee: CITIBANK, F.S.B. 500 WEST MADISON STREET
• Original Assignee: Transaction Technologies Incorporated (Citigroup Incorporated)
• Inventors: Meguerdijan, Sarkis A., Weiss, Lawrence D., Takata, Melvin M., Kawan, Joseph C., Parekh, Dilip J., Marks, Harvey, Lee, Shan, Samulon, Alfred S., Caruthers, Douglas W., Tucci, Morris L., Inatomi, Charles T., Vollmer, Jim R.
• Primary Examiner(s): Anderson, Lawrence E.
• Application Number:
  US07/260,832
• Time in Patent Office: 907 Days
• Field of Search: 379/110, 379/96, 379/97, 379/98, 364/200 MS File, 364/900 MS File, 364/110
• US Class Current: 379/110.01
• CPC Class Codes: G06Q 20/00 Payment architectures, schemes or protocols apparatus for performing or posting payment transactions G07F7/08, G07F19/00; electronic cash registers G07G1/12
• CPC Class Codes: H04M 1/2473 Telephone terminals interfacing a personal computer, e.g. using an API (Application Programming Interface) details of API H04M7/0021
• CPC Class Codes: H04M 11/066 Telephone sets adapted for data transmision

Abstract

The present invention relates to a programmable microcomputer or microprocessor device with associated memory and telephone circuitry designed to be operated in most circumstances through a standard telephone 12-key keypad input. The microcomputer device of the present invention, which includes the primary microprocessor operated in conjunction with other computer elements, including memory, has the overall appearance of a telephone. The primary microprocessor of the invention consists of a central processing unit and associated memory and includes enhanced integrity features. The device delivers data processing capabilities and services through an ordinary telephone instrument.

Claims

1. A microcomputer with simplified user interface including a microprocessor computing unit and associated memory;

said microprocessor computing unit responsive to data inputs from an auxiliary processor and instructions maintained in said memory and received through a modem to perform computing and control functions, said microprocessor computing unit and said memory mounted in a housing configured as a conventional telephone unit,

said housing having a upper mounting structure and a base structure, a telephone handset mounted in a cradle on said upper mounting structure, a standard twelve-key telephone keypad mounted on said upper mounting structure and a keyboard input device mounted in concealed position within said base structure and movable to an open position for use by the operator of the microcomputer;

said housing also incorporating telephone electronics for standard telephone functioning, including a telephone dialer, speech network and a frequency and ring detectors, said telephone electronics capable of being powered from standard telephone line power;

switch means for providing telephone line power to said telephone electronics for standard telephone functioning in the absence of power to or input from the microprocessor computing unit and memory;

a lapse timer reset by output from said microprocessor computing unit, said lapse timer means providing an interrupt to said microprocessor computing unit unless reset by said microprocessor computing unit within a first predetermined time interval, said microprocessor computing unit being rebooted and removing power from said telephone electronics and said lapse timer means being disabled unless said lapse timer means is reset with a second predetermined time interval; and

off-hook detector means for detecting an off-hook condition of said telephone handset mounted on said upper mounting structure, off-hook timer means responsive to said off-hook detector means and said microprocessor computing unit to reboot said microprocessor computing unit and remove power from said telephone electronics unless said off-hook timer is not reset by said microprocessor computing unit within a third predetermined time interval.

2. A microcomputer as claimed in claim 1 which further includes a parity check means for at least a part of the associated memory of the microprocessor computing unit of said microprocessor and logic means responsive to said parity check means to provide an interrupt to said microprocessor computing unit when said parity check means provides an error detection.

3. A microcomputer as claimed in claim 1 further including a dual output device for conventional twelve-key telephone keypad of said microcomputer for providing simultaneous outputs to the telephone dialer of said microcomputer and the microprocessor computing unit through a dual output element mounted below said keypad.

4. A microcomputer as claimed in claim 1 wherein the microprocessor computing unit of said microcomputer is responsive to inputs provided from the telephone electronics and provides control of said telephone electronics, the associated memory of said microprocessor computing unit incorporating both volatile and non-volatile elements so that said microprocessor computing unit and memory may be programmed as a general purpose computer, said memory including a removable memory element configured for permanent data storage even when removed from said microcomputer.