Passivation for integrated circuit structures

• US 5,010,024 A
• Filed: 05/15/1989
• Issued: 04/23/1991
• Est. Priority Date: 03/04/1987
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gwozdz, Peter S., Bowers, Thomas R., Allen, Bert L.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): OJAN, OURMAZD
• Application Number:
  US07/353,169
• Time in Patent Office: 708 Days
• Field of Search: 357/91, 357/52, 437/24, 437/52, 437/195
• US Class Current: 438/659
• CPC Class Codes: G11C 16/18 Circuits for erasing optically
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is described for producing an integrated circuit structure, including EPROMS, having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in an underlying metal layer in the structure, and, in the case of EPROMS, maintaining sufficient UV light transmissity to permit erasure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer to inhibit the formation of voids therein by implanting the metal layer with ions to change the grain structure adjacent the surface of the metal layer; forming an insulating intermediate layer between said the layer and the silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the compressive stress of the silicon nitride layer; and controlling the compressive stress in the silicon nitride layer to provide resistance to moisture and ion penetration superior to silicon dioxide or silicon oxynitride layers of similar thickness while inhibiting formation of voids in the metal layer.

Claims

1. A method for producing an integrated circuit structure encapsulated in a layer of silicon nitride to provide resistance to penetration by moisture and ion contaminants and further characterized by a substantial absence of observable voids in an underlying metal layer which comprises a portion of said integrated circuit structure, said method comprising the step of:

stress relieving the underlying metal layer from stresses induced by the compressive stress of said silicon nitride encapsulating layer by implanting the metal surface of said metal layer, before encapsulating said structure with said silicon nitride layer, with ions to change the grain structure adjacent the surface of said metal layer.

2. The method of claim 1 wherein said step of reducing the compressive stress in said silicon nitride layer further comprises lowering said compressive stress by maintaining, during formation of said silicon nitride layer, a pressure in the reactor high enough to maintain sufficient compressive stress to provide resistance to penetration by moisture and ion contaminants without resulting in the formation of ascertainable voids in said metal layer.

3. The method of claim 2 wherein said integrated circuit structure is an EPROM and said step of reducing the compressive stress in said silicon nitride layer in an amount sufficient, in combination with said implantation step, to eliminate the formation of acertainable voids in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants comprises forming said silicon nitride layer while maintaining a pressure in the reactor high enough to maintain sufficient compressive stress to provide resistance to penetration by moisture and ion contaminants without resulting in the formation of acertainable voids in said metal layer and to maintain sufficient Uv transparency in said silicon nitride layer to permit erasure of said EPROM in less than one hour at 0.02 to 0.03 watts/cm² intensity.

4. The method of claim 1 wherein said stress relief of said metal layer is accomplished by the steps of:

(a) implanting the metal surface of said metal layer with ions to change the grain structure adjacent the surface of said metal layer; and

(b) forming an intermediate stress-relieving layer between said metal layer and said silicon nitride encapsulating layer;

to eliminate the formation of ascertainable voids in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

5. The method of claim 1 wherein said stress relief of said metal layer is accomplishing by the stress of:

(a) forming an intermediate stress-relieving layer between said metal layer and said silicon nitride encapsulating layer; and

(b) reducing the compressive stress in said silicon nitride layer in an amount sufficient to eliminate the formation of ascertainable voids in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

10. The method of claim 1 wherein said step of stress relieving said underlying metal layer further comprises the steps of:

(a) implanting the metal surface of said metal layer, before encapsulating said structure with said silicon nitride layer, with ions to change the grain structure adjacent the surface of said metal layer by implanting, at an energy level of from about 40 kEV to about 200 kEV, ions selected from the class consisting of ions of argon, arsenic, boron, neon, krypton, silicon, by bombarding said metal layer with said ions at a concentration of from about 10¹⁵ to about 10¹⁶ ions/cm² to implant said ions into the surface of said metal layer to a depth of from about 150 to 2500Å

;

(b) forming an intermediate insulating layer consisting essentially of silicon oxynitride by chemically vapor depositing a mixture of silane and one or more oxides of nitrogen on said metal layer; and

(c) forming said silicon nitride layer in a reactor while maintaining a pressure in said reactor sufficient to provide a compressive stress in said silicon nitride layer of not less than 2.5×

10⁹ dynes/cm².

6. A method for producing an integrated circuit structure having improved resistance to penetration by moisture and ion contaminants and a substantial absence, in an underlying metal layer comprising a portion of said integrated circuit structure, of voids visible under a microscope, by stress relief of said metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer which comprises the steps of:

(a) implanting, to a depth of from about 150 to 2500Å

, the metal surface of said metal layer, before encapsulating said structure with said silicon nitride layer, with ions at an energy level of from about 40 KEV to about 200 KEV and a concentration of from about 10¹⁵ to about 10¹⁶ ions/cm² to change the grain structure adjacent the surface of said metal layer; and

(b) reducing the compressive stress in said silicon nitride layer to not less than 2.5×

10⁹ dynes/cm² but sufficient, in combination with said implantation step, to eliminate the formation of voids visible under a microscope in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

7. A method for producing an integrated circuit structure having improved resistance to penetration by moisture and ion contaminants and a substantial absence, in an underlying metal layer comprising a portion of said integrated circuit structure, of voids visible under a microscope, by stress relief of said metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer which comprises the steps of:

(a) implanting, to a depth of from about 150 to 2500Å

, the metal surface of said metal layer, before encapsulating said structure with said silicon nitride layer, with ions at an energy level of from about 40 KEV to about 200 KEV and a concentration of from about 10¹⁵ to about 10¹⁶ ions/cm² to change the grain structure adjacent the surface of said metal layer; and

(b) forming an intermediate stress-relieving layer between said metal layer and said silicon nitride encapsulating layer selected from the class consisting of silicon oxide and silicon oxynitride;

to eliminate the formation of voids visible under a microscope in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

8. The method of claim 7 wherein said step of forming said intermediate insulating layer further comprises forming an intermediate layer of silicon oxynitride by chemically vapor depositing a mixture of silane and one or more oxides of nitrogen on said metal layer while maintaining the concentration of said one or more oxides of nitrogen sufficiently high to lower the compressive stress in said silicon oxynitride layer to a level which will compensate for said compressive stress in the silicon nitride layer subsequently formed thereover to thereby inhibit formation of observable voids in said underlying metal layer.

9. The method of claim 8 wherein said stress relieving of said underlying metal layer further comprises reducing the compressive stress in said silicon nitride layer by forming said silicon nitride layer in a reactor while maintaining a pressure in said reactor sufficient to provide a compressive stress in said silicon nitride layer of not less than 2.5×

10⁹ dynes/cm².

11. A method for producing an integrated circuit structure having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in the underlying metal layer comprising a portion of said integrated circuit structure by stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer sufficiently to inhibit the formation of voids in said metal layer by the steps of:

(a) implanting the metal surface of said metal layer with ions to change the grain structure adjacent the surface of said metal layer; and

(b) reducing the compressive stress in said silicon nitride layer in an amount sufficient, in combination with said implantation step, to eliminate the formation of ascertainable voids in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

12. The method of claim 11 wherein said step of stress relieving said metal layer further includes the step of reducing the compressive stress in said silicon nitride layer to not less than 2.5×

10⁹ dynes/cm².

13. The method of claim 11 wherein said ion implantation step comprises implantation of ions into the surface of said metal to a depth of from about 150 to 2500Å

.

14. The method of claim 13 wherein said ion implantation step comprises implanting from about 10¹⁵ to about 10¹⁶ ions/cm² into the surface of said metal layer.

15. The system of claim 14 wherein said ion implantation step further comprised implanting said ions at an energy level of from about 40 kEV to about 200 kEV.

16. The method of claim 15 wherein said ion implantation step further comprises implanting ions selected from the class consisting of ions of argon, arsenic, boron, neon, krypton, silicon, and the metal being bombarded.

17. The system of claim 15 wherein said ion implantation step further comprises implanting argon ions into the surface of said metal layer.

18. A method for producing an integrated circuit structure having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in the underlying metal layer comprising a portion of said integrated circuit structure by stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer sufficiently to inhibit the formation of voids in said metal layer by the steps of:

(a) implanting the metal surface of said metal layer with ions to change the grain structure adjacent the surface of said metal layer; and

(b) forming an intermediate stress-relieving layer between said metal layer and said silicon nitride encapsulating layer;

to eliminate the formation of ascertainable voids in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

19. The method of claim 18 wherein said step of forming an intermediate stress-relieving layer further comprises forming an intermediate layer consisting essentially of a silicon oxide.

20. The method of claim 18 wherein said step of forming an intermediate insulating layer further comprises forming an intermediate insulating layer consisting essentially of silicon oxynitride.

21. The method of claim 20 wherein said step of forming said intermediate insulating layer consisting essentially of silicon oxynitride further comprises chemically vapor depositing a mixture of silane and one or more oxides of nitrogen on said metal layer while maintaining a pressure sufficiently high to compensate for said compressive stress in the silicon nitride layer subsequently formed thereover to inhibit formation of ascertainable voids in said underlying metal layer.

22. The method of claim 20 wherein said step of forming said intermediate insulating layer consisting essentially of silicon oxynitride further comprises chemically vapor depositing a mixture of silane and one or more oxides of nitrogen on said metal layer while maintaining the concentration of said one or more oxides of nitrogen sufficiently high to lower the compressive stress in said silicon oxynitride layer to a level which will compensate for said compressive stress in the silicon nitride layer subsequently formed thereover to thereby inhibit formation of ascertainable voids in said underlying metal layer.

23. The method of claim 21 including the further step of reducing the compressive stress in said silicon nitride layer in an amount sufficient, in combination with said step of forming said intermediate layer, to eliminate the formation of ascertainable voids in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

24. The method of claim 23 wherein said step of reducing the compressive stress in said silicon nitride comprises lowering said compressive stress of said silicon nitride layer to not less than 2.5×

10⁹ dynes/cm².

25. The method of claim 18 wherein said step of reducing the compressive stress in said silicon nitride comprises lowering said compressive stress of said silicon nitride layer to not less than 2.5×

10⁹ dynes/cm².

26. A method for producing an integrated circuit structure having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of ascertainable voids in an underlying metal layer comprising a portion of said integrated circuit structure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer by the steps of:

(a) implanting the metal surface of said metal layer with ions to change the grain structure adjacent the surface of said metal layer;

(b) forming an insulating intermediate layer between said metal layer and said silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the compressive stress of said silicon nitride layer to inhibit the formation of ascertainable voids in said metal layer; and

(c) controlling the compressive stress of said silicon nitride layer during formation of said layer by chemical vapor deposition of silane and ammonia to provide sufficient compressive stress to provide resistance to penetration by moisture and ion contaminants superior to silicon dioxide or silicon oxynitride layers of similar thickness while inhibiting, in combination with said intermediate layer, the inducement of sufficient stress in said metal layer to cause the formation of ascertainable voids in said metal layer.

27. A method for producing an erasable programmable read only memory type integrated circuit structure having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of ascertainable voids in an underlying metal layer comprising a portion of said integrated circuit structure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a UV light-transparent silicon nitride encapsulating layer by the steps of:

(a) implanting the metal surface of said metal layer with ions to change the grain structure adjacent the surface of said metal layer;

(b) forming a UV light-transparent insulating intermediate layer between said metal layer and said silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the compressive stress of said silicon nitride layer to inhibit the formation of ascertainable voids in said metal layer; and

(c) controlling the compressive stress of said silicon nitride layer formed by chemical vapor deposition of silane and ammonia to provide a compressive stress of at least 2.5×

10⁹ dynes/cm² to provide resistance to penetration by moisture and ion contaminants superior to silicon dioxide or silicon oxynitride layers of similar thickness while maintaining said UV light transparency of said silicon nitride layer and while inhibiting, in combination with said intermediate layer, the inducement of sufficient stress in said metal layer to cause the formation of ascertainable voids in said metal layer.

28. A method for producing an integrated circuit structure encapsulated in a layer of silicon nitride to provide resistance to penetration by moisture and ion contaminants and further characterized by a substantial absence of observable voids in an underlying metal layer which comprises a portion of said integrated circuit structure, said method comprising:

stress relieving said underlying metal layer from stresses induced by the compressive stress of said silicon nitride encapsulating layer to inhibit the formation of observable voids in said metal layer by the following steps;

(a) implanting the metal surface of said metal layer, before encapsulating said structure with said silicon nitride layer, with ions to change the grain structure adjacent the surface of said metal layer by implanting, at an energy level of from about 40 kEV to about 200 kEV, ions selected from the class consisting of ions of argon, arsenic, boron, neon, krypton, silicon, by bombarding said metal layer with said ions at a concentration of from about 10¹⁵ to about 10¹⁶ ions/cm² to implant said ions into the surface of said metal layer to a depth of from about 150 to 2500Å

;

(b) forming an intermediate insulating layer consisting essentially of silicon oxynitride by chemically vapor depositing a mixture of silane and one or more oxides of nitrogen on said metal layer; and

(c) forming said silicon nitride layer in a reactor while maintaining a pressure in said reactor sufficient to provide a compressive stress in said silicon nitride layer of not less than 2.5×

10⁹ dynes/cm².

29. A method for producing an integrated circuit structure having improved resistance to penetration by moisture and ion contaminants and a substantial absence, in an underlying metal layer comprising a portion of said integrated circuit structure, of voids visible under a microscope, by stress relief of said metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer which comprises the steps of:

(a) implanting, to a depth of from about 150 to 2500Å

, the metal surface of said metal layer, before encapsulating said structure with said silicon nitride layer, with ions at an energy level of from about 40 KEV to about 200 KEV and a concentration of from about 10¹⁵ to about 10¹⁶ ions/cm² to change the grain structure adjacent the surface of said metal layer; and

(b) reducing the compressive stress in said silicon nitride layer to not less than 2.5×

10⁹ dynes/cm² but sufficient, in combination with said implantation step, to eliminate the formation of voids visible under a microscope in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.

30. A method for producing an integrated circuit structure having improved resistance to penetration by moisture and ion contaminants and a substantial absence, in an underlying metal layer comprising a portion of said integrated circuit structure, of voids visible under a microscope, by stress relief of said metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer which comprises the steps of:

(a) implanting, to a depth of from about 150 to 2500Å

, the metal surface of said metal layer, before encapsulating said structure with said silicon nitride layer, with ions at an energy level of from about 40 KEV to about 200 KEV and a concentration of from about 10¹⁵ to about 10¹⁶ ions/cm² to change the grain structure adjacent the surface of said metal layer; and

(b) forming an intermediate stress-relieving layer between said metal layer and said silicon nitride encapsulating layer selected from the class consisting of silicon oxide and silicon oxynitride;

to eliminate the formation of voids visible under a microscope in said metal layer while still maintaining sufficient compressive stress in said silicon nitride layer to provide resistance to penetration by moisture and ion contaminants.