Time-key integrated circuit

• US 5,010,331 A
• Filed: 11/14/1989
• Issued: 04/23/1991
• Est. Priority Date: 03/02/1988
• Status: Expired due to Fees

• Current Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Lee, Robert D., Bolan, Michael L., Dias, Donald R., Scherpenberg, Francis A.
• Primary Examiner(s): Yusko, Donald J.
• Assistant Examiner(s): Pudpud, Eric O.
• Application Number:
  US07/437,012
• Time in Patent Office: 525 Days
• Field of Search: 340/825.3, 340/825.31, 340/825.32, 340/825.34, 340/825.83, 340/825.84, 340/825.69, 340/825.72, 361/172, 70/277, 70/278, 307/10.1, 307/465, 365/96, 235/389, 235/382, 235/382.5
• US Class Current: 340/5.28
• CPC Class Codes: G04F 1/005 using electronic timing, e.g. counting means pulse time delay arrangements H03K5/13; modifications of electronic switches for introducing a time delay before switching H03K17/28
• CPC Class Codes: G04G 3/02 Circuits for deriving low frequency timing pulses from pulses of higher frequency pulse frequency dividers in general H03K23/00 - H03K29/00
• CPC Class Codes: G07C 9/00857 where the code of the data carrier can be programmed
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

A secure electronic circuit which (in its early life) can be electronically calibrated and written to, but thereafter holds its data securely.

Claims

1. An electronic key, comprising:

a timing circuit which can be calibrated;

a fusing and detection circuit, comprising;

a fuse element;

a fuse input terminal, connected so that said fuse element can be blown by applying a large abnormal voltage to said fuse input terminal;

a comparator,

having first and second inputs operatively connected to said fuse element in such relation that

said first input of said comparator receives a voltage which is dependent on the state of said fuse element

and said second input of said comparator receives a voltage which is not substantially dependent on the state of said fuse element,

wherein said comparator compares said first and second inputs and provides a logic output which, in a first state, indicates that said fuse element has not been blown, and, in a second state, indicates that said fuse element has been blown;

wherein said fuse input terminal is operatively connected to said inputs of said comparator in such relation that any large abnormal voltage which is applied to said fuse input terminal will tend to drive the output of said comparator into said second state;

wherein said output of said comparator is connected to said timing circuit so that said second output state of said comparator prevents calibration of said timing circuit;

a counter, connected to count accesses to said electronic key;

control logic including a latch which can be set by receipt of a predetermined external command, said control logic being configured so that

at least some commands are accepted before said fuse element has been blown but are not accepted after said fuse element is blown;

at least some other commands are accepted after said fuse element has been blown and before said latch has been set, but are not accepted after said latch has been set; and

at least some other commands are accepted after said latch has been set and before said counter counts off a predetermined number of accesses, but are not accepted after said counter has counted said predetermined number of accesses;

wherein said latch cannot be reset after said fuse element has been blown;

and wherein said control logic and said counter are configured so that, if power is restored after said fuse element has already been blown, said counter will immediately provide an output indicating that said predetermined number of accesses has already occurred.