Insulator separated vertical CMOS

• US 5,010,386 A
• Filed: 12/26/1989
• Issued: 04/23/1991
• Est. Priority Date: 12/26/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Groover, Robert III
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): SAADAT, MAHSHID D
• Application Number:
  US07/457,030
• Time in Patent Office: 483 Days
• Field of Search: 357/42, 357/50, 357/41, 357/47, 357/49, 357/25, 357/41, 357/42, 357/55, 357/23.4, 357/23.6, 357/23.7
• US Class Current: 257/369
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of the first channel layer and an insulating layer is formed on the surface of the first source/drain layer. A second source/drain layer of the second conductivity type is formed on the surface of the insulating layer and a second channel layer of said first conductivity is formed on the surface of the second source/drain layer. A third source/drain layer of the second conductivity type is formed on the surface of the second channel layer. Gate circuitry is vertically disposed on an edge perpendicular to the plane and adjacent to the first and second channel layers and insulated therefrom.

Claims

1. A complementary semiconductor device structure comprising:

a substrate of a first conductivity type;

a first channel layer of a second conductivity type formed on the surface of said substrate;

a first source/drain layer of said first conductivity type formed on the surface of said first channel layer;

an insulating layer formed on the surface of said first source/drain layer;

a second source/drain layer of said second conductivity type formed on the surface of said insulating layer;

a second channel layer of said first conductivity type formed on the surface of said second source/drain layer;

a third source/drain layer of said second conductivity type formed on the surface of said second channel layer; and

gate circuitry vertically disposed on an edge perpendicular to the plane of and adjacent to said first and second channel layers, and insulated therefrom.

2. The semiconductor structure of claim 1 and further comprising a conductive region connected to said first source/drain layer and insulated from said second source/drain layer.

3. The semiconductor structure of claim 1 and further comprising a conductive region connected to said second source/drain layer and insulated from said first source/drain layer.

4. The semiconductor structure of claim 1 and further comprising a conductive region connected to said first and second source/drain layers.

5. The semiconductor structure of claim 1 wherein said gate circuitry comprises:

a first gate region defining a channel in said first conducting layer between said substrate and said first source/drain layer; and

a second gate regions defining a channel in said second conducting layer between said second and third source/drain layers.

6. The semiconductor structure of claim 5 wherein said first conductivity type comprises P type conductivity and said second conductivity type comprises an N type conductivity type.

7. The semiconductor structure of claim 1 wherein said source/drain and channel layers are laterally isolated to define a hexagonal semiconductor mesa.

16. The semiconductor structure of claim 1, wherein said complimentary semiconductor device structure is connected in a circuit other than a CMOS inventor.

8. A semiconductor device comprising:

a substrate;

monocrystalline semiconductor mesas at the surface of the substrate;

a first thin film conductive layer disposed below the surface of said mesas at a first predetermined depth to provide an electrical connection to predetermined ones of said mesas; and

a second thin film conductive layer disposed below the surface of said mesas at a second predetermined depth to provide an electrical connection to predetermined ones of said mesas, said second contact electrically insulated from said first contact.

9. The semiconductor device of claim 8 wherein said mesa comprises first and second vertical transistors separated by an insulating layer.

10. The semiconductor device of claim 9 wherein said first contact is coupled to a source/drain of said first vertical transistor and said second source/drain is connected to a source/drain of said second vertical transistor.

11. The semiconductor device of claim 9 wherein said first vertical transistor comprises an N-channel transistor.

12. The semiconductor device of claim 11 wherein said second vertical transistor comprises a P-channel transistor.

13. The semiconductor device of claim 12 wherein said N-channel transistor is disposed above said P-channel transistor.

14. The semiconductor device of claim 8 wherein said mesa comprises a hexagonal-shaped mesa.

15. The semiconductor device of claim 14 wherein said first and second contacts comprise hexagonal-shaped contacts.