Neural network having an associative memory that learns by example

• US 5,010,512 A
• Filed: 01/12/1989
• Issued: 04/23/1991
• Est. Priority Date: 01/12/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hartstein, Allan M., Koch, Roger H.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Trammell, Jim
• Application Number:
  US07/296,111
• Time in Patent Office: 831 Days
• Field of Search: 364/807, 364/602, 364/513, 364/131, 364/200 MS File, 364/900 MS File, 307/201
• US Class Current: 706/18
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A neural network utilizing the threshold characteristics of a semiconductor device as the various memory elements of the network. Each memory element comprises a complementary pair of MOSFETs in which the threshold voltage is adjusted as a function of the input voltage to the element. The network is able to learn by example using a local learning algorithm. The network includes a series of output amplifiers in which the output is provided by the sum of the outputs of a series of learning elements coupled to the amplifier. The output of each learning element is the difference between the input signal to each learning element and an individual learning threshold at each input. The learning is accomplished by charge trapping in the insulator of each individual input MOSFET pair. The thresholds of each transistor automatically adjust to both the input and output voltages to learn the desired state. After input patterns have been learned by the network, the learning functions is set to zero so that the thresholds remain constant and the network will come to an equilibrium state under the influence of a test input pattern thereby providing, as an output, the learned pattern most closely resembling the test input pattern.

Claims

1. A neural network comprising;

a matrix of a plurality of output electrodes intersecting with a plurality of input electrodes at intersecting regions, and a plurality of electronic elements coupling said output electrodes to said input electrodes at said intersecting regions;

means interconnecting said electronic elements such that input signals are continuously processed by said electronic elements;

each of said electronic elements comprising an analog threshold device in which its output voltage increases substantially symmetrically in both the positive and negative directions from a threshold voltage as a function of its input voltage.

2. The neural network of claim 1 wherein the output voltage of each said threshold device increases substantially linearly in both the positive and negative directions from said threshold voltage as a function of its input voltage.

3. The neural network of claim 2 wherein each said threshold device includes means for adjusting the threshold voltage in response to a change in its input voltage.

4. The neural network of claim 3 wherein each said threshold device includes means for adjusting its threshold voltage proportional to the difference between its output voltage and its input voltage.

5. The neural network of claim 4 wherein said interconnecting means interconnects said threshold devices such that the output voltage of each said threshold device is proportional to the difference between its input voltage and a threshold voltage at its input.

6. The neural network of claim 5 wherein each said threshold device comprises a complementary pair of field effect transistors connected in parallel, the gates of said pair being connected together to an input terminal, the drains of said pair being connected together to an output terminal and the sources of said pair being connected together to a fixed potential.

7. The neural network of claim 6 wherein each said output electrode includes an output means, a plurality of said complementary pairs of FETs being connected in parallel to each said output electrode such that all the output terminals of said pairs of FETs are coupled to the output means of said output electrodes, the input terminal of each said pair of FETs being connected to one of said input electrodes, the input voltage applied to each input terminal of each said pair of FETs being a voltage from one of said output means.

8. The neural network of claim 7 wherein each said output electrode has an output voltage proportional to the sum of the output voltage of each threshold device connected to said output electrode of the form:

##EQU3## where;

V_i^L =the output voltage of the ith output electrode;

V_j =the input voltage applied to the jth input electrode;

Ti_j =the threshold voltage of the threshold device connecting the jth input electrode to the ith output electrode;

a=constant equal to the gain of the threshold devices connected to the ith output electrode;

i=l to M;

j=l to N;

M=total number of output electrodes;

N=total number of input electrodes.

9. The neural network of claim 7 wherein said proportional relationship between the input and output voltages of each threshold device is of the form ##EQU4## where;

v_i^L =the output voltage of the ith output electrode;

V_j =the input voltage applied to the jth input electrode;

T_ij =the threshold voltage of the threshold device connecting the jth input electrode to the ith output electrode;

a=a constant equal to the gain of the threshold devices connected to the ith output electrode;

i=l to M;

j=l to N;

M=total number of output electrodes;

N=total number of input electrodes.

10. The neural network of claims 7 or 8 wherein each of said threshold devices having a threshold voltage adjustable in accordance with the function:

space="preserve" listing-type="equation">T.sub.ij.sup.* =T.sub.ij +α

(|V.sub.j -V.sub.i |-β

)

where;

T_ij^* =the new threshold voltage;

T_ij =the former threshold voltage;

α

=constant that sets the adjustment rate;

β

=constant that ensure symmetry in the adjustment;

V_i =the output voltage of the output means.

11. The neural network of claim 10 wherein each said output means is a threshold output amplifier.

12. The neural network of claim 11 wherein each said output amplifier has an input-output voltage characteristic such that for an input greater than a certain value, the output will be high and for an input less than said certain value, the output will be low.

13. The neural network of claim 11 wherein each said output amplifier has an input-output voltage characteristic such that for an input greater than a certain value, the output is low and for an input less than said certain value, the output is high.

14. The neural network of claim 10 wherein each of said FETs comprising each said complementing pair of FETs is a MOSFET having a gate insulator layer in which charge is trapped in said insulator layer at a rate equal to α

(V_G -β

) upon the application of a voltage V_G to the gate of (V_j -V_i) and charge leaks out of said insulator layer at a rate α

β

when voltage is removed from the gate.

15. A neural network suitable for information processing, comprising:

means for outputting a plurality of network output voltages, each of said network output voltages being the sum of the outputs of a series of learning elements having an adjustable threshold value as a memory means, the input of each respective learning element being a respective one of said network output voltages;

the output of each learning element being proportional to its input voltage minus a learned threshold value at its input, the output voltage having a functional relationship with respect to the input voltage which is symmetric and monotonically increasing about said threshold value;

the threshold value being adjustable as a function of the input voltage of the learning element and its corresponding network output voltage in a learning mode, the functional relationship being of the form;

space="preserve" listing-type="equation">T.sub.ij.sup.* =T.sub.ij +α

(|V.sub.j -V.sub.i -β

)

where,

T_ij^* =the new threshold value;

T_ij =the former threshold value;

α

=a learning rate constant;

β

=a learning step;

V_i =the ith network output voltage;

V_j =the jth input voltage of the network;

i=l to M;

j=l to N;

M=total number of output means;

N=total number of input electrodes.

means for selectively setting α

to zero so that the threshold value remains constant in an associative memory mode;

whereby said neural network operates in said learning mode wherein in response to a pattern of desired output signals applied to the network, the threshold value of each learning element continually adjusts such that the threshold value of each element represents the learned states that will provide the desired output pattern in response to a given input pattern; and

said neural network operates in said associative memory mode wherein the threshold values remain constant and the output of each learning element reaches a steady state that is only dependent upon the input signals of a test input pattern such that the output voltages of the network provide the desired learned output pattern most closely related to the test input pattern.

16. The neural network of claim 15 wherein said means for outputting a plurality of network output voltages includes a plurality of output amplifiers, each output amplifier being coupled to one of said series of learning elements, each of said learning elements comprising a complementary pair of multigate FETs connected in parallel.

17. The neural network of claim 16 wherein each of said pair of multigate FETs include common drain and source regions and an equal number of gates, the drain regions of each multigate FET being coupled to a corresponding output amplifier and the source regions being coupled to a fixed potential, each respective gate of one multigate FET being coupled to a corresponding respective gate of the other multigate FET of said pair, thereby forming a respective input terminal for each learning element of said series of learning elements.

18. The neural network of claim 17 wherein the sum of the output voltages of each learning element in each series of learning elements is of the form:

##EQU5## where, a is a constant set by the gain of the learning elements.

19. The neural network of claim 17 wherein the sum of the output voltages of each learning element in each series of learning element is of the form:

##EQU6## where a is a constant set by the gain of the learning elements.

20. The neural network of claim 17 wherein said output amplifier has an input-output voltage characteristic such that for an input greater than a certain value, the output will be high and for an input less than said certain value, the output will be low.

21. The neural network of claim 17 wherein said output amplifier has an input-output voltage characteristic such that for an input greater than a certain value, the output is low and for an input less than said certain value, the output is high.

22. The neural network of claim 17 wherein said FETs are MOSFETs having a gate insulator in which charge is trapped in said insulator layer at a rate equal to α

(V_G -β

) upon the application of a voltage V_G to the gate of (V_j -V_i) and charge leaks out of said insulator layer at a rate α

β

when voltage is removed from the gate.

23. A memory element of an artificial neuron comprising:

a complementary pair of field effect transistors connected in parallel, the gates of said pair being connected together to an input terminal, the drains of said pair being connected together to an output terminal and the sources of said pair being connected together to a fixed potential, the output voltage of said memory element increasing substantially symmetrically in both the positive and negative direction from a threshold voltage as a function of the input voltage of said memory element.

24. The memory element of claim 23 wherein the output voltage of said memory element increases substantially linearly in both the positive and negative directions from said threshold voltage as a function of its input voltage.

25. The memory element of claim 24 including means for adjusting the threshold voltage of said memory element in response to a change in its input voltage.

26. The memory element of claim 25 including means for adjusting the threshold voltage of said memory element proportional to the difference between its output voltage and its input voltage.

27. The memory element of claim 26 wherein the threshold voltage of said memory element is adjustable in accordance with the function:

space="preserve" listing-type="equation">T.sub.ij.sup.* =T.sub.ij +α

(|V.sub.j -V.sub.i |-β

)

where;

T_ij^* =the new threshold voltage;

T_ij =the former threshold voltage;

α

=constant that sets the adjustment rate;

β

=constant that ensure symmetry in the adjustment;

V_j =input voltage of the element;

V_i =output voltage of the element.

28. The memory element of claim 27 wherein each of said FETs comprising said complementing pair of FETs is a MOSFET having a gate insulator layer in which charge is trapped in said insulator layer at a rate equal to α

(V_G -β

) upon the application of a voltage V.sub. to the gate of (V_j -V_i) and charge leaks out of said insulator layer at a rate α

β

when voltage is removed from the gate.