Nonvolatile semiconductor memory device with stabilized data write characteristic

• US 5,010,520 A
• Filed: 07/27/1988
• Issued: 04/23/1991
• Est. Priority Date: 07/29/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakai, Hiroto, Tatsumi, Yuuichi, Asano, Masamichi, Iwahashi, Hiroshi, Minagawa, Hidenobu, Imai, Mizuho
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/224,953
• Time in Patent Office: 1,000 Days
• Field of Search: 365/174, 365/182, 365/185, 365/189.11, 365/189.01, 365/148, 357/23.6, 307/36, 307/38
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Claims

1. A nonvolatile semiconductor memory device comprising:

a power source;

a nonvolatile memory cell transistor having a drain and a source;

a load transistor having a drain, a source, and a gate, said source of said load transistor being coupled to said drain of said memory cell transistor, said drain of said load transistor being connected to said power source, and said gate of said load transistor being coupled for reception of an input data signal; and

a wiring layer connected in series to a path of said drain and said source of said load transistor and between said power source and said drain of said memory cell transistor, resistance of said wiring layer being larger than a resistance of said load transistor when said load transistor is turned on.

2. The memory device according to claim 1, in which said wiring layer is a polysilicon layer.

3. The memory device according to claim 1, in which said wiring layer is an impurity diffusion layer.

4. The memory device according to claim 1, further comprising a column select transistor connected between said load transistor and said memory cell.

5. The memory device according to claim 1, in which said wiring layer is inserted between said power source and said load transistor.

6. The memory device according to claim 4, in which said wiring layer is inserted between said column select transistor and said load transistor.

7. The memory device according to claim 4, in which said wiring layer is inserted between said column select transistor and said memory cell.

8. A nonvolatile semiconductor memory device comprising:

a power source;

a nonvolatile memory cell transistor having a drain and a source;

a load transistor having a drain, a source, and a gate, said source of said load transistor being coupled to said drain of said memory cell transistor, said drain of said load transistor being connected to said power source, and said gate of said load transistor being coupled for reception of an input data signal;

a column select transistor having a drain and a source whose path is connected between a path of said drain and said source of said load transistor and a path of said drain and said source of said memory cell transistor; and

a wiring layer connected in series to a path of said drain and said source of said load transistor and between said power source and said drain of said memory cell transistor, resistance of said wiring layer being larger than a resistance of said load transistor when said load transistor is turned on, said wiring layer being laid on a field region adjacent that of said column select transistor.

9. The memory device according to claim 8, in which said wiring layer is a pollysilicon layer.

10. The memory device according to claim 8, in which said wiring layer is an impurity diffusion layer.

11. The memory device according to claim 8, in which said wiring layer is inserted between said power source and said load transistor.

12. The memory device according to claim 8, in which said wiring layer is inserted between said column select transistor and said load transistor.

13. The memory device according to claim 8, in which said wiring layer is inserted between said column select transistor and said memory cell.

14. A nonvolatile semiconductor memory device comprising:

a plurality of memory cell circuits each including

a nonvolatile memory cell transistor having a drain and a source whose path is connected to a reference voltage via a conductive layer having a resistance; and

a plurality of semiconductor elements connected in series between a power source voltage and the path of the drain and the source of the memory cell transistor, including

a load transistor coupled with the power source voltage and coupled at the gate with an input data signal,

a column select transistor coupled with the memory cell transistor and coupled at the gate with a column select signal,

and a resistor, connected between the load transistor and the column select transistor,

wherein the resistor in at least one of the memory cell circuits has a resistance that is different from that of the resistor in another memory cell circuit, and which is selected according to the resistance of the conductive layer.

15. The memory device according to claim 14, in which said resistor is a polysilicon layer.

16. The memory device according to claim 14, in which said resistor is an impurity diffusion layer.

17. A nonvolatile semiconductor memory device comprising:

a plurality of memory cell circuits each including

a nonvolatile memory cell transistor having drain and a source whose path is connected to a reference voltage via conductive layer having a resistance; and

a plurality of semiconductor elements connected in series between a power source voltage and the path of the drain and the source of the memory cell transistor, including

a load transistor coupled with the power source voltage and coupled at the gate with an input data signal,

a column select transistor coupled with the load transistor and coupled at the gate with a column select signal, and

a resistor connected between the column select transistor and the memory cell transistor,

wherein the resistor in at least one of the memory cell circuits has a resistance that is different from that of the resistor in another memory cell circuit, and which is selected according to the resistance of the conductive layer.

18. A nonvolatile semiconductor memory device comprising:

a plurality of memory cell circuits each including

a nonvolatile memory cell transistor having drain and a source whose path is connected to a reference voltage via conductive layer having a resistance; and

a plurality of semiconductor elements connected in series between a power source voltage and the path of the drain and the source of the memory cell transistor, including

a load transistor coupled with the power source voltage and coupled at the gate with an input data signal, and

a column select transistor coupled with the memory cell transistor and coupled at the gate with a column select signal,

wherein the column select transistor in at least one of the memory cell circuits has a resistance that is different from that of the column select transistor in another memory cell circuit, and which is selected according to the resistance of the conductive layer.

19. A nonvolatile semiconductor memory device comprising:

a plurality of memory cell circuits each including

a nonvolatile memory cell transistor having drain and a source whose path is connected to a reference voltage via conductive layer having a resistance; and

a plurality of semiconductor elements connected in series between a power source voltage and the path of the drain and the source of the memory cell transistor, including

a load transistor coupled with the power source and coupled at the gate with an input data signal, and

a column select transistor coupled with the memory cell transistor and coupled at the gate with a column select signal,

wherein the load transistor in at least one of the memory cell circuits has a resistance that is different from that of the load transistor in another memory cell circuit, and which is selected according to the resistance of the conductive layer.

20. A nonvolatile semiconductor memory device comprising:

a plurality of memory cell circuits each including;

a nonvolatile memory cell transistor having drain and a source whose path is connected to a reference voltage via a conductive layer having a resistance; and

a plurality of semiconductor elements connected in series between a power source voltage and the path of the drain and the source of the memory cell transistor, including

a load transistor coupled with the power source voltage and coupled at the gate with an input data signal,

a column select transistor coupled with the memory cell transistor and coupled at the gate with a column select signal, and

a resistor, connected between the load transistor and the column select transistor, composed of an impurity diffusion layer,

wherein the resistor in at least one of the memory cell circuits has a resistance that is different from that of the resistor in another memory cell circuit, and which is selected according to the resistance of the conductive layer.

21. A nonvolatile semiconductor memory device comprising:

a plurality of memory cell circuit each including

a nonvolatile memory cell transistor having drain and a source whose path is connected to a reference voltage via a conductive layer having a resistance; and

a plurality of semiconductor elements connected in series between a power source voltage and the path of the drain and the source of the memory cell transistor, including

a load transistor coupled with the power source voltage and coupled at the gate with an input data signal,

a column select transistor coupled with the memory cell transistor and coupled at the gate with a column select signal, and

a resistor, connected between the load transistor and the column select transistor, composed of a polysilicon layer,

wherein the resistor in at least one of the memory cell circuits has a resistance that is different from that of the resistor in another memory cell circuit, and which is selected according to the resistance of the conductive layer.