Method of reworking an electrical multilayer interconnect

• US 5,011,580 A
• Filed: 06/25/1990
• Issued: 04/30/1991
• Est. Priority Date: 10/24/1989
• Status: Expired due to Fees

• Current Assignee: Microelectronics and Computer Technology Corporation
• Original Assignee: Microelectronics and Computer Technology Corporation
• Inventors: Pan, Ju-Don T., Schultz, Laurence D., Curry, John W. II
• Primary Examiner(s): TUFARIELLO, THOMAS
• Application Number:
  US07/543,317
• Time in Patent Office: 309 Days
• Field of Search: 204/15, 204/38.1, 204/38.4, 204/40
• US Class Current: 205/118
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/072 Electroless plating, e.g. finish plating or initial plating
• CPC Class Codes: H05K 2203/0733 Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/222 Completing of printed circuits by adding non-printed jumper connections printed jumper connections H05K3/4685
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4647 by applying an insulating layer around previously made via studs

Abstract

A method of reworking an electrical multilayer interconnect in which the electrical lines can be protected by an overcoat. The method includes removing a defective metallization layer from the top of an interconnect substrate, depositing an electrically conductive layer on the substrate, forming a base plating mask on the electrically conductive layer, plating a copper base into an opening in the base plating mask onto the electrically conductive layer, stripping the base plating mask, forming a pillar plating mask on top of the copper base, plating an electrically conductive metal pillar into an opening in the pillar plating mask onto the top of the copper base, stripping the plating mask, and stripping the electrically conductive layer below the stripped base plating mask. Additionally, a protective overcoat layer can be deposited on the exposed copper surfaces.

Claims

1. A method of reworking an electrical multilayer interconnect comprising:

removing a defective metallization layer from the top of an interconnect substrate,

depositing an electrically conductive layer on the substrate,

forming a base plating mask on the electrically conductive layer,

plating a copper base into an opening in the base plating mask onto the electrically conductive layer,

stripping the base plating mask,

forming a pillar plating mask on top of the copper base,

plating an electrically conductive metal pillar into an opening in the pillar plating mask onto the top of the copper base,

stripping the pillar plating mask, and

stripping the electrically conductive layer below the stripped base plating mask.

2. The method of claim 1 wherein the electrically conductive layer is a metal.

3. The method of claim 2 wherein the electrically conductive metal layer is sputter deposited.

4. The method of claim 2 wherein the electrically conductive metal layer is electrolessly deposited.

5. The method of claim 1 wherein the electrically conductive metal pillar is plated by electroless deposition.

6. The method of claim 1 wherein the electrically conductive metal pillar is plated by electroplating.

7. The method of claim 1 wherein the electrically conductive metal pillar is selected from the group consisting of copper, nickel, and a nickel alloy.

8. The method of claim 1 further comprising the step of depositing an overcoat layer on the exposed copper surfaces.

9. The method of claim 8 wherein the overcoat layer is deposited on the exposed surfaces of the copper base and electrically conductive metal pillar.

10. The method of claim 8 wherein the overcoat layer is electrolessly deposited.

11. The method of claim 10 wherein the overcoat layer is an electrolessly deposited metal selected from the group consisting of chromium, nickel, and a nickel alloy.

12. The method of claim 8 wherein the overcoat layer is immersion coated.

13. The method of claim 12 wherein the overcoat layer is immersion coated tin.

14. The method of claim 8 wherein prior to depositing the overcoat layer a light copper etch is applied to the exposed copper surfaces.

15. The method of claim 1 wherein the defective metallization layer is removed by uniform and non-selective polishing.

16. The method of claim 15 wherein the polishing is done by a rotating pad with a slurry.

17. The method of claim 1 further including depositing a polyimide coating over the substrate after stripping the electrically conductive layer.

18. A method of reworking an electrical multilayer interconnect comprising:

removing a defective metallization layer from the top of an interconnect substrate,

depositing an electrically conductive metal layer on the substrate,

forming a base plating mask on the metal layer,

plating a copper base into an opening in the base plating mask onto the metal layer,

stripping the base plating mask,

forming a pillar plating mask on top of the copper base,

plating a pillar selected from the group consisting copper, nickel, and a nickel alloy into an opening in the pillar plating mask onto the top of the copper base,

stripping the pillar plating mask, and

stripping the metal layer below the stripped base plating mask.

19. The method of claim 18 further comprising the step of depositing an overcoat layer on the exposed copper surfaces.

20. The method of claim 19 wherein the overcoat layer is electrolessly deposited.

21. The method of claim 19 wherein the overcoat layer is immersion coated.

22. The method of claim 18 wherein the defective metallization layer is removed by uniform and non-selective polishing.

23. The method of claim 22 wherein the polishing is done by a rotating pad with a slurry.

24. The method of claim 18 further including depositing a polyimide coating over the substrate after stripping the metal layer.