System for testing internal nodes

• US 5,012,180 A
• Filed: 05/17/1988
• Issued: 04/30/1991
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: Smith, Don, Dalrymple, Monte J., Brubaker, Lois F.
• Primary Examiner(s): Wieder, Kenneth
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/194,857
• Time in Patent Office: 1,078 Days
• Field of Search: 324/73 R, 324/158 R, 324/73 AT, 371/20, 371/15, 371/25, 371/21, 371/22.1, 437/8
• US Class Current: 324/73.1
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.

Claims

1. In an integrated circuit device having internal data and address buses respectively connectable to external data and address buses, and having normally accessible internal nodes addressable by normal addresses from the external address bus, the improvement comprising a test mode means (100, 111, 121) in the integrated circuit device for enabling external access of predetermined and normally inaccessible internal test nodes in the integrated circuit device, said test mode means comprising:

a test mode decode means (103) responsive to an address from the external address bus for outputting a control signal to set the integrated circuit device in either a normal state or a test mode state, the normal state resulting from the address being one of the normal addresses and the test mode state resulting from the address being a predetermined address for initiating a test mode;

a test mode control register means (105) for storing an address of a predetermined internal test node, said address being obtainable from the external data bus;

a multiplexer means (101) responsive to the control signal for connecting the internal address bus (102) to the external address bus for receiving the normal addresses when in the normal state, and connecting to the test mode control register means for receiving the address of a predetermined internal test node when in the test mode state; and

test node decoder means (111,

     121) responsive to the control signal and the address of the predetermined internal test node for enabling the transfer of test data from the predetermined internal test node to the internal data bus, thereby allowing the normally inaccessible test node to be accessible from outside the device.

2. The test mode means of claim 1, further comprising an encoder which receives DMA access and channel select signals from an external control bus, said encoder generating a signal for inhibiting the test mode even when the control signal corresponds to that of the test mode state.

3. The test mode means of claim 1, wherein said test node decoder means includes at least one test write decoder for enabling the writing of data from the internal data bus into the selected internal nodes.

4. The test mode means of claim 1, wherein said test node decoder means includes at least one test read decoder for enabling the reading of data from the selected internal nodes onto the internal data bus.

5. The test mode means of claim 1, wherein said predetermined internal test node is that of a FIFO.

6. The test mode means of claim 1, wherein said predetermined internal test node is that of a cyclic redundancy check generator.

7. The test mode means of claim 1, wherein said predetermined internal test node is that of a clock signals multiplexer.

8. A test mode means included in an integrated circuit device for testing internal nodes in the integrated circuit device, said integrated circuit device being in communication with a microprocessor through an internal address bus, an external address bus and a data bus, and having device memory connected to the internal bus for storing data, said test mode means comprising:

storage means for storing an address of a selected internal test node in the device, said internal test node being other than that of the device memory, and said address of the selected internal test node being obtainable from the external data bus;

means responsive to a test command for selecting the address of the selected internal test node stored in the storage means and for supplying said address of the selected internal test node to the internal address bus; and

test node decoder means responsive only to the address of the selected internal test node on the internal address bus for enabling the transfer of data between the selected internal test node and the data bus for testing the selected internal test node.

9. The test mode means of claim 8, wherein said selecting means includes:

a test mode decode means for changing the value of a test mode in responsive to the test command; and

a multiplexer means for connecting the internal address bus either to an external bus or to the storage means, said multiplexer connecting the internal address bus to the storage means when the test mode signal is of a first value and connecting the internal address bus to the external bus when the test mode signal is of a second value.

10. The test mode means of claim 9, further comprising an encoder which receives DMA access and channel select signals from an external control bus, said encoder generating a signal for inhibiting the test mode even when the test mode signal is of the first value.

11. The test mode means of claim 8, wherein said test node decoder means includes at least one test write decoder for enabling the writing of data from the bus into the selected internal nodes.

12. The test mode means of claim 8, wherein said test node decoder means includes at least one test read decoder for enabling the reading of data from the selected internal nodes onto the data bus.

13. The test mode means of claim 8, wherein said selected internal test node is that of a FIFO.

14. The test mode means of claim 8, wherein said selected internal test node is that of a cyclic redundancy check generator.

15. The test mode means of claim 8, wherein said selected internal test node is that of a clock signals multiplexer.

16. The test mode means of claim 8, wherein said selecting means includes:

a test mode decode means for generating a select signal in response to the test command; and

a multiplexer means for connecting the internal address bus either to an external bus or to the storage means, said multiplexer connecting the internal address bus to the storage means when the select signal is of a first value and connecting the internal address bus to the external bus when the select signal is of a second value.