Integral switched capacitor FIR filter/digital-to-analog converter for sigma-delta encoded digital audio

• US 5,012,245 A
• Filed: 10/04/1989
• Issued: 04/30/1991
• Est. Priority Date: 10/04/1989
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.), Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Viswanathan, Thayamkulangara R., Scott, Jeffrey W.
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Young, Brian K.
• Application Number:
  US07/417,219
• Time in Patent Office: 573 Days
• Field of Search: 341/118, 341/120, 341/121, 341/144, 341/150, 341/153, 341/154, 341/172
• US Class Current: 341/150
• CPC Class Codes: G11B 20/10527 Audio or video recording; Data buffering arrangements G11B20/12 - G11B20/18 take precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03H 2021/0096 with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; anti-aliasing
• CPC Class Codes: H03H 21/0007 comprising switched capacitor [SC] devices
• CPC Class Codes: H03M 3/504 the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC

Abstract

A combined finite impulse response filter and digital-to-analog converter for converting sigma-delta over-sampled data into analog form. The filter removes out-of-band noise energy from the reconstructed analog signal resulting from the sigma-delta encoding process. The filter/converter is implemented in switched-capacitor technology. Further, a method of designing the optimum number of taps and the tap weight coefficients of the filter is given.

Claims

1. In an integrated circuit, a circuit for converting single bit digital input data into analog form, characterized by:

a shift register, having N-taps, for shifting the digital input data;

a plurality of signal capacitors, corresponding to the taps on the shift register, each signal capacitor having a predetermined capacitance and one end coupling to a summing node; and

,

a 2×

2 switch, responsive to the corresponding tap on the shift register, having two inputs for selectively coupling one of two voltage references to the other end of the signal capacitors depending on the state of the corresponding tap of the shift register and two outputs;

a 2;

1 switch for coupling the corresponding one of the plurality of signal capacitors to either of the outputs of the 2×

2 switch in response to the state of a clock signal;

wherein signals on the summing node are analog signals corresponding to the digital input data and the capacitances of the signal capacitors represent corresponding tap weight coefficients of a finite impulse response filter.

2. The circuit as recited in claim 1, further characterized by:

an inverting low-pass filter with a virtual ground input, referenced to a third voltage reference, and an output; and

,

a switch means for alternately coupling the summing node to the virtual ground input of the inverting low-pass filter and to the third voltage reference in response to the clock signal;

wherein the analog output of the circuit is the output of the inverting low-pass filter.

3. The circuit as recited in claim 2, wherein the voltage of the third voltage reference is substantially the same as the voltage of the second voltage reference.

4. A method of converting single bit digital input data into analog form characterized by the steps of:

shifting the digital input data with a multiple tap shift register;

summing to a summing node charge from a plurality of signal capacitors, corresponding to the taps on the shift register, each signal capacitor having a predetermined capacitance; and

,

switching with a 2×

2 switch, in response to the corresponding tap of the shift register, one of two voltage references between two outputs of the 2×

2 switch depending on the state of the corresponding tap of the shift register; and

,

switching the corresponding signal capacitor between the two outputs of the 2×

2 switch in response to a clock signal;

wherein signals on the summing node are analog signals corresponding to the digital input data and the capacitances of the signal capacitors represent corresponding tap weight coefficients of a finite impulse response filter.

5. The method as recited in claim 4, further comprising the step of:

filtering the signals on the summing node with a low-pass filter.

6. A method of determining the number of taps and the tap weight coefficients in a filter adapted to filter over-sampled data, characterized by the steps of:

generating a digital data stream from an encoder, used to encode the over-sampled data, with no signal input;

generating a sampled signal representing the passband of the desired filter;

combining the digital data stream and the sampled signal;

filtering the combined digital data stream and the sampled signal by the filter;

subtracting the output of the filter from a delayed version of the sampled signal to form an error signal, the amount of delay being substantially the same as the delay through the filter; and

,

adjusting the number of taps and the tap weight coefficients of the filter to reduce the error signal.

7. The method as recited in claim 6, wherein the step of generating a sampled signal is further characterized by the steps of:

generating a plurality of sampled sinusoids, the frequencies of which are within the desired passband of the filter, and,

combining the sampled sinusoids to create the sampled signal.

8. The method as recited in claim 7, wherein the step of adjusting the number of taps and the tap weight coefficients uses the least-mean-squares minimization process.

9. The method as recited in claim 8, wherein the filter is a finite impulse response filter.