Split-gate field effect transistor

• US 5,012,315 A
• Filed: 01/09/1989
• Issued: 04/30/1991
• Est. Priority Date: 01/09/1989
• Status: Expired due to Term

• Current Assignee: Regents of The University of Minnesota (University of Minnesota)
• Original Assignee: Regents of The University of Minnesota (University of Minnesota)
• Inventors: Shur, Michael
• Primary Examiner(s): Prenty, Mark
• Application Number:
  US07/295,083
• Time in Patent Office: 841 Days
• Field of Search: 357/23.12, 357/23.14, 357/16, 357/91
• US Class Current: 257/365
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/8124 with multiple gate

Abstract

A field effect transistor having a gate voltage swing in the transistor channel varying as a function of position between the drain and the source. The gate voltage swing in the transistor channel may be made to vary as a function of position by making the threshold voltage a function of position. Alternatively, a split-gate device may be used by applying a voltage between the gates. In both cases, the electric field near the source is raised to accelerate the electrons thereby decreasing electron transit time.

Claims

1. A method of decreasing carrier transit time in a transistor including a drain region, a single conducting channel region, a source region, and first and second gate contacts overlying the channel region, comprising the steps of:

applying an electric field to the single conducting channel region by applying voltages to the gate contacts which overlie the channel region in a single plane; and

varying a vector component of the electric field in the channel region in a direction from the source region to the drain region as a function of position in the direction from the source region to the drain region by applying a first voltage to the first gate contact overlying the channel region and separated from the channel region by an insulator which has an insulator thickness and applying a second voltage to the second gate contact overlying the channel region and separated from the channel region by the insulator, wherein the first voltage is different from the second voltage and the first and second gate contacts are separated from each other by a distance generally less than the insulator thickness.

2. A field effect transistor comprising:

a drain source region including a drain contact;

a source region including a source contact;

a channel region extending between the drain region and the source region;

a plurality of gate contacts overlying the channel region in a single plane, each gate contact of the plurality of gate contacts is electrically isolated from the other gate contacts and is generally separated from the channel region by an insulating layer having an insulator thickness between a gate contact and the channel region, and wherein adjacent gate contacts of the plurality of gate contacts are separated from each other by a distance generally less than the insulator thickness between a gate contact and the channel region; and

means for applying a plurality of different voltages to the plurality of gate contacts.

3. The field effect transistor of claim 2 wherein the insulating layer is AlGaAs.