Board wiring pattern for a high density memory module

• US 5,012,389 A
• Filed: 12/14/1988
• Issued: 04/30/1991
• Est. Priority Date: 12/14/1988
• Status: Expired due to Term

• Current Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Original Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Inventors: Perry, Richard A.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Sparks, Donald A.
• Application Number:
  US07/284,238
• Time in Patent Office: 867 Days
• Field of Search: 361/398, 361/399, 361/406, 361/409, 361/410, 361/416, 307/89, 174/250, 174/253, 174/254, 174/255, 174/261, 324/174, 324/173, 324/719, 73/766, 73/708, 364/900, 364/922.7, 357/68, 357/74, 357/75, 357/45, 333/161
• US Class Current: 361/679.31
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: H05K 1/0296 Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/18 Printed circuits structurally associated with non-printed electric components H05K1/0201, H05K1/023, H05K1/0243, and H05K1/16 take precedence
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09227 Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/09263 Meander
• CPC Class Codes: H05K 2201/09772 Conductors directly under a component but not electrically connected to the component
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2201/10522 Adjacent components
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A high density memory module in which memory chips are mounted in an array of rows and columns on a printed circuit board. The circuit board includes groups of serpentine parallel conductors which extend along adjacent columns for connecting corresponding power, ground, control, address and data pins between the adjacent columns to one another. Adjacent groups of serpentine parallel conductors are nested within one another. According to the invention, high density packaging is provided for large chip arrays, using a minimum number to vias to interior board layers, and minimum interchip spacing.

Claims

1. A memory module comprising:

a plurality of memory chips and a mounting surface therefor, each chip including a plurality of signal pins for power, ground, control, address and data signals and at least one enable pin for selecting said chip, said memory chips being mounted on said mounting surface in an array of at least three rows and a plurality of columns;

said mounting surface including a group of serpentine parallel conductors extending along two adjacent columns in the at least three rows of said array, which connect the corresponding signal pins between the two adjacent columns in the at least three rows to one another.

3. The memory module of claim 1 wherein said mounting surface includes a plurality of groups of serpentine parallel conductors, with a respective group extending along respective adjacent columns in the at least three rows of said array, which connect the corresponding signal pins between each of said respective adjacent columns in the at least three rows to one another, with the serpentine patterns along said respective adjacent columns being nested within one another.

4. The memory module of claim 1 wherein said mounting surface is a printed circuit board.

2. A memory module comprising:

a plurality of memory chips and a mounting surface therefor, each chip including a plurality of signal pins for power, ground, control, address and data signals and at least one enable pin for selecting said chip, said memory chips being mounted on said mounting surface in an array of rows and columns;

said mounting surface including a group of serpentine parallel conductors extending along two adjacent columns in said array, which connect the corresponding signal pins between the two adjacent columns to one another;

wherein said memory chips are packaged in normal and reverse pin configurations, the normal pin configuration comprising said plurality of signal pins and said at least one enable pin in a counterclockwise arrangement, and the reverse pin configuration comprising said plurality of signal pins and said at least one enable pin in a clockwise arrangement; and

wherein said columns of said array comprise alternating normal and reverse pin chips, and said at least three rows of said array comprise alternating normal and reverse pin chips in alternating 180°

rotations.

5. A memory module comprising:

a plurality of memory chips and a mounting surface therefor, each chip including a plurality of signal pins for power, ground, control, address and data signals and at least one enable pin for selecting said chip, said memory chips being mounted on said mounting surface in an array of rows and columns;

said mounting surface including a first pattern of concentric conductors which connect the signal pins on one end of a first chip with corresponding signal pins on said one end of the chip below said first chip; and

a second pattern of concentric conductors which connect the signal pins on the opposite end of said first chip with the corresponding signal pins on the opposite end of the chip above said first chip;

said first pattern lying under said first chip and said chip below said first chip, and said second pattern lying under said first chip and said chip above said first chip.

6. The memory module of claim 5 wherein said one end is the left end and wherein said opposite end is the right end of the respective ones of said chips.

8. The memory module of claim 5 wherein said mounting surface is a printed circuit board.

7. A memory module comprising:

a plurality of memory chips and a mounting surface therefor, each chip including a plurality of signal pins for power, ground, control, address and data signals and at least one enable pin for selecting said chip, said memory chips being mounted on said mounting surface in an array of rows and columns;

said mounting surface including a first pattern of concentric conductors which connect the signal pins on one end of a first chip with corresponding signal pins on said one end of the chip below said first chip; and

a second pattern of concentric conductors which connect the signal pins on the opposite end of said first chip with the corresponding signal pins on the opposite end of the chip above said first chip;

said first pattern lying under said first chip and said chip below said first chip, and said second pattern lying under said first chip and said chip above said first chip;

wherein said memory chips are packaged in normal and reverse pin configurations, the normal pin configuration comprising said plurality of signal pins and said at least one enable pin in a counterclockwise arrangement, and the reverse pin configuration comprising said plurality of signal pins and said at least one enable pin in a clockwise arrangement; and

wherein said columns of said array comprise alternating normal and reverse pin chips, and said rows of said array comprise alternating normal and reverse pin chips in alternating 180°

rotations.

9. A memory module comprising:

a plurality of memory chips and a mounting surface therefor, each chip including a plurality of signal pins for power, ground, control, address and data signals and at least one enable pin for selecting said chip, said memory chips being mounted on said mounting surface in an array of rows and columns;

said mounting surface including a first serpentine pattern of parallel conductors which connect corresponding ones of said signal pins on one end of a first chip to the opposite end of a second chip in the same row and previous column as said first chip, to the opposite end of a third chip in the next row and same column as said second chip, to the one end of a fourth chip in the same row and next column as said third chip, to the one end of a fifth chip in the same column and next row as said fourth chip, and to the opposite end of a sixth chip in the same row and previous column as said fifth chip.

10. The memory module of claim 9 wherein said one end is the left end and wherein said opposite end is the right end of the respective ones of said chips.

11. The memory module of claim 9 wherein said memory chips are packaged in normal and reverse pin configurations, the normal pin configuration comprising said plurality of signal pins and said at least one enable pin in a counterclockwise arrangement, and the reverse pin configuration comprising said plurality of signal pins and said at least one enable pin in a clockwise arrangement;

and wherein said columns of said array comprise alternating normal and reverse pin chips and said rows of said array comprise alternating normal and reverse pin chips in alternating 180°

rotations.

12. The memory module of claim 9 wherein said mounting surface includes a second serpentine pattern of parallel conductors which connect corresponding ones of said signal pins on the opposite end of said first chip to the one end of a seventh chip in the same row and next column as said first chip to the opposite end of said fourth chip, to the one end of an eighth chip in the same row and next column as said fourth chip, to the one end of a ninth chip in the same column and next row as said eighth chip, and to the opposite end of said fifth chip.

13. The memory module of claim 12 wherein said one end is the left end and wherein said opposite end is the right end of the respective ones of said chips.

14. The memory module of claim 12 wherein said first and second serpentine patterns are nested within one another.

15. The memory module of claim 9 wherein said mounting surface is a printed circuit board.

16. A memory module comprising:

a plurality of memory chips and a mounting surface therefor, each chip including a plurality of signal pins for power, ground, control, address and data signals and at least one enable pin for selecting said chip, said memory chips being mounted on said mounting surface in an array of rows and columns;

said mounting surface including a plurality of parallel conductors connecting the signal pins at one end of each chip with corresponding ones of the signal pins at the adjacent end of the chip in the previous column and the same row; and

connecting the signal pins at the other end of each chip with the corresponding ones of the signal pins at the adjacent end of the chip in the next column and the same row;

said mounting surface further including a first pattern of concentric conductors connecting the signal pins at said one end of each chip with corresponding ones of the signal pins at said one end of the chip in the next row of the same column, said first pattern of concentric conductors lying under the two chips which are connected thereby; and

a second pattern of concentric conductors connecting the signal pins at said other end of each chip with corresponding ones of the signal pins said one end of the chip in the previous row of the same column, said second pattern of concentric conductors lying under the two chips which are connected thereby.

17. The memory module of claim 16 wherein said memory chips are packaged in normal and reverse pin configurations, the normal pin configuration comprising said plurality of signal pins and said at least one enable pin in a counterclockwise arrangement, and the reverse pin configuration comprising said plurality of signal pins and said at least one enable pin in a clockwise arrangement;

and wherein said columns of said array comprise alternating normal and reverse pin chips, and said rows of said array comprise alternating normal and reverse pin chips in alternating 180°

rotations.

18. The memory module of claim 16 wherein said first and second patterns are nested within one another.

19. The memory module of claim 16 wherein said mounting surface is a printed circuit board.

20. A mounting surface for memory chips comprising:

a plurality of chip sites, each including a plurality of signal pads for power, ground, control, address and data signals and at least one enable pad, said memory chip sites being arranged on said mounting surface in an array of at least three rows and a plurality of columns; and

a group of serpentine parallel conductors extending along two adjacent columns in the at least three rows of said array, which connect the corresponding signal pads between the two adjacent columns in the at least three rows to one another.

21. The mounting surface of claim 20 wherein said mounting surface includes a plurality of groups of serpentine parallel conductors, with a respective group extending along respective adjacent columns in the at least three rows of said array, which connect the corresponding signal pads between each of said respective adjacent columns in the at least three rows to one another, with the serpentine patterns along said respective columns being nested within one another.

22. The mounting surface of claim 20 wherein said mounting surface is a printed circuit board.

23. A mounting surface for memory chips comprising:

a plurality of chip sites, each including a plurality of signal pads for power, ground, control, address and data signals and at least one enable pad, said memory chip sites being arranged on said mounting surface in an array of rows and columns; and

a first pattern of concentric conductors which connect the signal pads on one end of a first chip site with corresponding signal pads on said one end of the chip site below said first chip site; and

a second pattern of concentric conductors which connect the signal pads on the opposite end of said first chip site with the corresponding signal pads on the opposite end of the chip site above said first chip site;

said first pattern lying on said first chip site and said chip site below said first chip site, and said second pattern lying on said first chip site and said chip site above said first chip site.

24. The mounting surface of claim 23 wherein said mounting surface is a printed circuit board.

25. The mounting surface of claim 23 wherein said one end is the left end and said opposite end is the right end of the respective ones of said chip sites.

26. A mounting surface for memory chips comprising:

a plurality of chip sites, each including a plurality of signal pads for power, ground, control, address and data signals and at least one enable pad, said memory chip sites being arranged on said mounting surface in an array of rows and columns; and

a first serpentine pattern of parallel conductors which connect corresponding ones of said signal pads on one end of a first chip site to the opposite end of a second chip site in the same row and previous column as said first chip site, to the opposite end of a third chip site in the next row and same column as said second chip site, to the one end of a fourth chip site in the same row and next column as said third chip site, to the one end of a fifth chip site in the same column and next row as said fourth chip site, and to the opposite end of a sixth chip site in the same row and previous column as said fifth chip site.

27. The mounting surface of claim 26 wherein said one end is the left end and said opposite end is the right end of the respective ones of said chip sites.

31. The mounting surface of claim 26 wherein said mounting surface is a printed circuit board.

28. A mounting surface for memory chips comprising:

a plurality of chip sites, each including a plurality of signal pads for power, ground, control, address and data signals and at least one enable pad, said memory chip sites being arranged on said mounting surface in an array of rows and columns;

a first serpentine pattern of parallel conductors which connect corresponding ones of said signal pads on one end of a first chip site to the opposite end of a second chip site in the same row and previous column as said first chip site, to the opposite end of a third chip site in the next row and same column as said second chip site, to the one end of a fourth chip site in the same row and next column as said third chip site, to the one end of a fifth chip site in the same column and next row as said fourth chip site, and to the opposite end of a sixth chip site in the same row and previous column as said fifth chip site; and

a second serpentine pattern of parallel conductors which connect corresponding ones of said signal pads on the opposite end of said first chip site to one end of a seventh chip site in the same row and next column as said first chip site, to the opposite end of said fourth chip site to the one end of an eighth chip site in the same row and next column as said fourth chip site, to the one end of a ninth chip site in the same column and next row as said eighth chip site, and to the opposite end of said fifth chip site.

29. The mounting surface of claim 28 wherein said one end is the left end and said opposite end is the right end of the respective ones of said chip sites.

30. The mounting surface of claim 28 wherein said first and second serpentine patterns are nested within one another.

32. A mounting surface for memory chips comprising:

a plurality of chip sites each including a plurality of signal pads for power, ground, control, address and data signals and at least one enable pad, said chip sites being arranged on said mounting surface in an array of rows and columns;

a plurality of parallel conductors connecting the signal pads at one end of each chip site with corresponding ones of the signal pads at the adjacent end of the chip site in the previous column and the same row; and

connecting the signal pads at the other end of each chip site with the corresponding ones of the signal pads at the adjacent end of the chip site in the next column and the same row; and

a first pattern of concentric conductors connecting the signal pads at said one end of each chip site with corresponding ones of the signal pads at said one end of the chip site in the next row of the same column, said first pattern of concentric conductors lying on the two chip sites which are connected thereby; and

a second pattern of concentric conductors connecting the signal pads at said other end of each chip site with corresponding ones of the signal pads said one end of the chip site in the previous row of the same column, said second pattern of concentric conductors lying on the two chip sites which are connected thereby.

33. The mounting surface of claim 32 wherein said first and second patterns are nested within one another.

34. The mounting surface of claim 32 wherein said mounting surface is a printed circuit board.