Semiconductor integrated circuit and method of manufacturing the same

• US 5,012,427 A
• Filed: 01/30/1989
• Issued: 04/30/1991
• Est. Priority Date: 01/30/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kuribayashi, Mototaka
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/303,261
• Time in Patent Office: 820 Days
• Field of Search: 364/491, 364/490, 364/489, 364/488, 307/480, 307/269, 307/270
• US Class Current: 716/110
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A semiconductor integrated circuit device comprises a plurality of cell arrays including at least one cell array having main and one feed-through cells, and a plurality of clock driver cells provided on the cell arrays. The feed-through cells are selectively connected to the clock driver cells so that loads imposed to the clock driver cells are made substantially uniform.

Claims

1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

forming, on a semiconductor chip, a plurality of cell arrays including at least one cell array having at least one main cell and at least one feed-through cell;

arranging a plurality of clock driver cells on said plurality of cell arrays so that at least one of said clock driver cells is provided in each of said cell arrays;

determining the number of said main cells in each of said cell arrays which are to be driven by said clock driver cells;

detecting the maximum number of said main cells which it is determined are to be driven in the above step;

calculating the difference between the detected maximum number of said main cells and the total number of said main cells included in each of said cell arrays; and

connecting, to said clock driver cells, said feed-through cells, the number of which corresponds to the calculated difference, so that loads imposed on said clock driver cells are made substantially uniform.

2. The method according to claim 1, wherein said step for arranging said clock driver cells includes a step of arranging a plurality of clock driver cells on each of said cell arrays, and a step of selectively allocating a plurality of regions of each of said cell arrays to said clock driver cells included in the corresponding cell array.

3. The method according to claim 1, wherein said step of arranging said clock driver cells includes a step of obtaining the other difference between the difference and the number of feed-through cells, and a step of arranging additional feed-through cells on the corresponding cell array when the number of feed-through cells is less than the other difference.

4. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

forming, on a semiconductor chip, a plurality of basic-cell arrays including a plurality of basic cells having logical and non-logical cells;

arranging a plurality of clock driver cells on said plurality of basic-cell arrays so that at least one of said driver cells is provided in each of said basic-cell arrays;

determining the number of said logical cells to be driven by each of said clock driver cells;

detecting the maximum number of the logical cells which it is determined are to be driven in said above step;

calculating a difference between the detected maximum number of logical cells and the total number of said basic cells included in each of said basic-cell arrays; and

connecting, to said clock driver cells, said non-logical cells, the number of which corresponds to the calculated difference, so that loads imposed to said clock driver cells are made substantially uniform.

5. The method according to claim 4, wherein said step of forming a plurality of basic-cell arrays includes a step of arranging said basic cells in a matrix, and said step of connecting said non-logical cells to said clock driver cells includes a step of connecting said clock driver cells to said basic cells of said basic-cell arrays which are adjacent to each of said clock driver cells and are used as a wiring region.

6. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

forming, on a semiconductor chip, a plurality of cell arrays each having at least one main cell and a plurality of feed-through cells over which signal lines are selectively run;

arranging a plurality of clock driver cells on said plurality of cell arrays so that at least one of said clock driver cells is provided in each of said cell arrays;

determining the number of said main cells in each of said cell arrays which are to be driven by each of said clock driver cells;

detecting the maximum number of said main cells which it is determined are to be driven in the above step;

calculating the difference between the detected maximum number of said main cells and the total number of said main cells included in each of said cell arrays; and

connecting, to said clock driver cells, said feed-through cells, the number of which corresponds to the calculated difference, so that loads imposed on said clock driver cells are made substantially uniform.

7. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

forming, on a semiconductor chip, a plurality of cell arrays including at least one cell array having at least one main cell and at least one feed-through cell;

arranging a plurality of clock driver cells on each of said plurality of cell arrays;

selectively allocating a plurality of regions of each of said cell arrays to said clock driver cells included in the corresponding cell array;

determining the number of said main cells to be driven by each of said clock driver cells;

detecting the maximum number of said main cells which it is determined are to be driven in the above step;

calculating the difference between the detected maximum number of said main cells and the total number of said main cells included in each of said cell arrays; and

connecting, to said clock driver cells, said feed-through cells, the number of which corresponds to the calculated difference, so that loads imposed to said clock driver cells are made substantially uniform.

8. The method according to claim 7, wherein said step of arranging a plurality of clock driver cells includes a step of determining the other difference between the difference and the number of feed-through cells, and a step of arranging additional feed-through cells on the corresponding cell array, when the number of feed-through cells is less than the other difference.

9. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

forming, on a semiconductor chip, a plurality of basic-cell arrays including a plurality of basic cells having logical and non-logical cells;

arranging a plurality of clock driver cells on said plurality of basic-cell arrays;

determining the number of said logical cells to be driven by each of said clock driver cells;

detecting the maximum number of logical cells which it is determined are to be driven in said above step;

calculating a difference between the detected maximum number of logical cells and the total number of said basic cells included in each of said basic-cell arrays; and

connecting, to said clock driver cells, said non-logical cells, the number of which corresponds to the calculated difference, so that loads imposed on said clock driver cells are made substantially uniform.

10. The method according to claim 9, wherein the step of forming a plurality of basic-cell arrays includes a step of arranging said basic cells in a matrix, and the step of connecting said non-logical cells to said clock driver cells includes a step of connecting said clock driver cells to said basic cells of said basic-cell arrays which are adjacent to each of said clock driver cells and are used as a wiring region.