Apparatus for addressing memory with data word and data block reversal capability

• US 5,012,441 A
• Filed: 11/24/1986
• Issued: 04/30/1991
• Est. Priority Date: 11/24/1986
• Status: Expired due to Term

• Current Assignee: Zoran Corporation (Qualcomm, Inc.)
• Original Assignee: Zoran Corporation (Qualcomm, Inc.)
• Inventors: Retter, Refael
• Primary Examiner(s): Lee, Thomas C.
• Application Number:
  US06/933,815
• Time in Patent Office: 1,618 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/726, 377/41, 377/69, 377/52, 377/55
• US Class Current: 711/217
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 7/768 Data position reversal, e.g. bit reversal, byte swapping

Abstract

Memory address generation circuitry includes two binary counters for generating addresses for application to an address bus. The least significant bits of one counter are connected to the address bus in bit positions corresponding to the most significant bits of the other counter whereby the two counters increment addresses in opposite directions. The mode of address generation permits addresses for data in normal order, data within data blocks in normal order and data blocks in reverse-bit order, and data within data blocks in bit-reverse order and data blocks in normal order. The circuitry has particular applicability in memory address generation when operating on data with algorithms for FFT operations in one or more dimensions.

Claims

1. Memory addressing circuitry comprising:

a first binary counter comprising a plurality of serially connected binary cells,

a second binary counter comprising a plurality of serially connected binary cells,

a first bus for loading a count into said first and second binary counters,

an address bus for receiving count from said first and second counters, said binary cells of said counters being connected to said address bus whereby the least significant bits of one counter correspond to the most significant bits of the other counter whereby addresses from said two counters increment in opposite directions, and address mode means for controlling the application of addresses from said first and second binary counters to said address bus.

2. The circuitry as defined by claim 1 wherein addresses from said counters can include a data block address and a data word address within a data block, said address mode means controlling addresses to said address bus to represent data in normal order, data within blocks in normal order and data blocks in bit-reverse order, and data within blocks in bit-reverse order and blocks in normal order.

3. The circuitry as defined by claim 2 wherein said address mode means include a programmed logic array for controlling block address and data word address generation from said first and second binary counters.