Cell capacitor of a dynamic random access memory and a method of manufacturing the same

• US 5,013,679 A
• Filed: 09/05/1989
• Issued: 05/07/1991
• Est. Priority Date: 09/09/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshikawa, Susumu, Kumagai, Jumpei
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/403,292
• Time in Patent Office: 609 Days
• Field of Search: 437/38, 437/47, 437/51, 437/52, 437/60, 437/83, 437/89, 437/99, 437/228, 437/203, 437/233, 437/235, 437/919, 357/23.6, 357/51
• US Class Current: 438/388
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

In a cell capacitor of a dynamic random access memory cell according to the present invention, an insulation film is formed on the surface of a fine trench formed in a silicon semiconductor substrate. A contact hole is formed in the insulation film in a region on the side wall of the trench. A polysilicon film is formed on the side wall of the trench in a hollow-cylindrical shape. A silicon layer is epitaxially and selectively grown on the polysilicon film and on the silicon substrate exposed through the contact hole. The polysilicon film and the silicon layer constitute an information storage electrode. At least the silicon layer of the information storage electrode is electrically connected to a source or a drain region of a transfer transistor of the memory cell. A gate insulation film is formed on the surface of the silicon layer. A counter electrode is formed such that the counter electrode is embedded in the trench.

Claims

1. A method of manufacturing a cell capacitor of a dynamic random access memory, comprising the steps of:

forming a trench in a semiconductor substrate;

exposing a portion of said semiconductor substrate, which is located in a region on a side wall of said trench;

forming a semiconductor layer on the side wall of said trench;

causing an electrically conductive layer to be epitaxially and selectively grown only on said semiconductor layer and on the exposed portion of said semiconductor substrate, and integrating said electrically conductive layer during the growth;

forming a gate insulation film on a surface of said electrically conductive layer; and

forming a counter electrode on said gate insulation film and within said trench.

2. The method according to claim 1, wherein said semiconductor layer has an electrical conductivity.

3. The method according to claim 1, wherein said trench includes a hole.

4. The method according to claim 1, wherein said trench includes a groove.

5. The method according to claim 1, wherein said region on the side wall of the trench includes a plurality of areas, and said electrically conductive layer is formed by epitaxial growth on said semiconductor substrate opening to said plurality of areas on the side wall of the trench, and on said semiconductor layer.

6. The method according to claim 1, wherein said region on the side wall of the trench includes a single area, and said electrically conductive layer is formed by epitaxial growth on said semiconductor substrate opening to said single area on the side wall of the trench, and on said semiconductor layer.

7. A method of manufacturing a cell capacitor of a dynamic random access memory, comprising the steps of:

forming a trench in a semiconductor substrate;

forming an insulation film on an inner surface of said trench;

forming a semiconductor layer on a side wall of said trench;

exposing a portion of said semiconductor substrate, which is located in a region on an upper surface of the semiconductor substrate in the vicinity of said trench;

causing an electrically conductive layer to be epitaxially and selectively grown only on said semiconductor layer and on the exposed portion of said semiconductor substrate, and integrating said electrically conductive layer during the growth;

forming a gate insulation film on the surface of said electrically conductive layer; and

forming a counter electrode on said gate insulation film and within said trench.

8. The method according to claim 7, wherein said semiconductor layer has an electrical conductivity.

9. The method according to claim 7, wherein said trench includes a hole.

10. The method according to claim 7, wherein said trench includes a groove.

11. The method according to claim 7, wherein said region on the upper surface of the semiconductor substrate in the vicinity of said trench includes the entire peripheral region of a verge of an opening of the trench, and said electrically conductive layer is formed by epitaxial growth on said entire peripheral region of the verge of the opening of the trench, which is located on the upper surface of the semiconductor substrate, and on said semiconductor layer.

12. The method according to claim 7, wherein said region on the upper surface of the semiconductor substrate in the vicinity of said trench includes a portion of the peripheral region of a verge of an opening of the trench, and said electrically conductive layer is formed by epitaxial growth on said portion of the peripheral region of the verge of the opening of the trench, which is located on the upper surface of the semiconductor substrate, and on said semiconductor layer.