CMOS integrated circuit with EEPROM and method of manufacture
First Claim
1. An integrated circuit comprising:
- a substrate of a semiconductor material having a surface;
an MOS transistor in said substrate at said surface and having a gate electrode with a feature size of no greater than about two microns and having a maximum voltage capability; and
an EEPROM in said substrate at said surface, said EEPROM being capable of being programmed at voltages which are compatible with the maximum voltage capability of the MOS transistor, and the EEPROM having a control gate and a floating gate with a ratio of capacitance of the floating gate to control gate to capacitance of the floating gate to substrate of at least about two.
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Accused Products
Abstract
The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors. Additional steps are inserted in the standard CMOS process to form the EEPROM. The additional steps are inserted in such a manner so as not to adversely affect the operating characteristics of the resulting MOS transistors. For this purpose, any additional steps for forming the EEPROM which are carried out at a temperature of greater than 900° C. are done so before the gate silicon dioxide layer of the MOS transistors is formed, and any further steps of forming the EEPROM are carried out at temperatures no greater than 900° C.
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Citations
7 Claims
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1. An integrated circuit comprising:
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a substrate of a semiconductor material having a surface; an MOS transistor in said substrate at said surface and having a gate electrode with a feature size of no greater than about two microns and having a maximum voltage capability; and an EEPROM in said substrate at said surface, said EEPROM being capable of being programmed at voltages which are compatible with the maximum voltage capability of the MOS transistor, and the EEPROM having a control gate and a floating gate with a ratio of capacitance of the floating gate to control gate to capacitance of the floating gate to substrate of at least about two. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit comprising:
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a substrate of a semiconductor material having a surface; a pair of complementary MOS transistors in said substrate at said surface with each having a gate electrode feature size no greater than about two microns and also having a maximum voltage capability; and an EEPROM in said substrate at said surface, said EEPROM being capable of being programmed at voltages which are compatible with the maximum voltage capability of the complementary MOS transistors, and the EEPROM having a control gate and a floating gate with a ratio of capacitance of the floating gate to control gate to capacitance of a floating gate to substrate of at least about two.
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7. An integrated circuit comprising:
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a substrate of a semiconductor material having a surface; a plurality of complementary MOS transistors in said substrate at said surface with each using two micron or less design having a gate electrode feature size no greater than about two microns and also having a reverse break-down voltage and a maximum voltage capability; and a plurality of EEPROM units in said substrate at said surface, each said EEPROM unit capable of being programmed at voltages which are within the reverse break-down voltage of the complementary MOS transistors, and each EEPROM unit has a control gate and a floating gate with a ratio of capacitance of the floating gate to control gate to capacitance of a floating gate to substrate of at least about two, effective to provide an IC with high-speed complementary MOS transistor logic and also with EEPROM units that are programmable with voltages compatible with the maximum voltage capability of the high-speed complementary MOS transistors.
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Specification