Signal level control circuit having alternately switched capacitors in the feedback branch

• US 5,014,130 A
• Filed: 07/24/1990
• Issued: 05/07/1991
• Est. Priority Date: 07/31/1989
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Jann, Wolfango, Heister, Heinz
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Powell, Mark R.
• Application Number:
  US07/557,532
• Time in Patent Office: 287 Days
• Field of Search: 358/168, 358/170, 358/171, 358/172, 358/173, 358/34, 358/174, 358/178
• US Class Current: 348/687
• CPC Class Codes: H04N 5/20 Circuitry for controlling amplitude response

Abstract

A circuit for controlling the amplitude of video signals includes a control circuit which contains a first capacitor. For each image pulse, a charge which corresponds to the amplitude of the generated video signal during a prior frame cycle is stored in the first capacitor. During the frame flyback pulse, this charge is transferred to a second capacitor by means of a switch. The second capacitor'"'"'s voltage serves as a control voltage for the video signal. After the charge is transferred to the second capacitor, the first capacitor is discharged.

Claims

1. An amplitude controlling circuit for video signals output on a video signal path, the video signals providing image frequency pulses during a frame flyback sequence, comprising:

(a) a first control device coupled in line with the video signal path and having a video signal output;

(b) a second control device providing an actual value of an input signal to said first device, the input signal being derived from the video signal output;

(c) a first capacitor charged by the video signal;

(d) a first switch coupled in parallel with the first capacitor;

(e) a second capacitor having a charging voltage substantially equal to the actual value of the input signal;

(f) a second switch coupled in series between the first and second capacitors wherein at least two consecutive control pulses are generated from the image frequency pulses, the first of said control pulses closing the second switch while the first switch is open and the second of said control pulses closing the first switch while the second switch is open.

2. The circuit according to claim 1, further comprising:

a first monostable element having an input which receives the image frequency pulses and an output which provides a control input for the second switch;

a time delay element receiving the image frequency pulses from the first monostable element; and

a second monostable element receiving the image frequency pulses from the time delay element and providing an output to a control input of the first switch.

3. The circuit according to claim 2, wherein a gate circuit has a first input coupled to the output of the first monostable element and a second input which receives a control signal supplied to block the signals of the first monostable element, the gate circuit being arranged to provide the control input for the second switch.

4. The circuit according to claim 3, further comprising video equipment operating in an interleaved scanning according to the manner and generating image frequency pulses including frame flyback pulses or pulses derived therefrom;

the control signal of the gate circuit operating to block every other pulse generated by the first monostable element.